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kasjer pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
The following commit(s) were added to refs/heads/master by this push:
new cdc2b9332 mcu/stm32h5: Configure drive strength for LSE
cdc2b9332 is described below
commit cdc2b93326bab0f596cf62b3922e24ec172d4d3f
Author: Jerzy Kasenberg <[email protected]>
AuthorDate: Fri Sep 25 10:55:08 2026 +0200
mcu/stm32h5: Configure drive strength for LSE
It turned out that default value for drive capability
LL_RCC_LSEDRIVE_LOW (0) is not supported for most
of STM32H5 devices.
Default register value 0 result in LSE not starting
sometimes on some device or at all on others.
Now code changes drive capability when LSE is enabled.
Errata sheet states:
LSE low drive mode is not functional.
Now this value is syscfg configurable
and default value is set to MEDIUMLOW.
Signed-off-by: Jerzy Kasenberg <[email protected]>
---
hw/mcu/stm/stm32h5xx/src/clock_stm32h5xx.c | 4 ++++
hw/mcu/stm/stm32h5xx/syscfg.yml | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/hw/mcu/stm/stm32h5xx/src/clock_stm32h5xx.c
b/hw/mcu/stm/stm32h5xx/src/clock_stm32h5xx.c
index 828d5bf32..d31080a04 100644
--- a/hw/mcu/stm/stm32h5xx/src/clock_stm32h5xx.c
+++ b/hw/mcu/stm/stm32h5xx/src/clock_stm32h5xx.c
@@ -99,7 +99,9 @@ SystemClock_Config(void)
LL_RCC_LSE_EnableBypass();
}
if (MYNEWT_VAL_STM32_CLOCK_LSE && !LL_RCC_LSE_IsReady()) {
+ LL_RCC_LSE_Disable();
LL_PWR_EnableBkUpAccess();
+
LL_RCC_LSE_SetDriveCapability(MYNEWT_VAL_STM32_CLOCK_LSE_DRIVE_CAPABILITY);
LL_RCC_LSE_Enable();
}
if (MYNEWT_VAL_STM32_CLOCK_HSE_BYPASS) {
@@ -206,6 +208,8 @@ SystemClock_Config(void)
LL_RCC_SetSPIClockSource(LL_RCC_SPI1_CLKSOURCE_CLKP);
LL_RCC_SetSPIClockSource(LL_RCC_SPI2_CLKSOURCE_CLKP);
LL_RCC_SetSPIClockSource(LL_RCC_SPI3_CLKSOURCE_CLKP);
+
+ BUSY_LOOP(MYNEWT_VAL_STM32_CLOCK_LSE && !LL_RCC_LSE_IsReady());
}
#endif
diff --git a/hw/mcu/stm/stm32h5xx/syscfg.yml b/hw/mcu/stm/stm32h5xx/syscfg.yml
index 2a647af1b..da2928399 100644
--- a/hw/mcu/stm/stm32h5xx/syscfg.yml
+++ b/hw/mcu/stm/stm32h5xx/syscfg.yml
@@ -54,6 +54,10 @@ syscfg.defs:
description: 0 for 32768 xtal; 1 for input clock
value: 0
+ STM32_CLOCK_LSE_DRIVE_CAPABILITY:
+ description: LSE drive capability.
+ value: LL_RCC_LSEDRIVE_MEDIUMLOW
+
STM32_CLOCK_HSE:
description: Enable high-speed external clock source
value: 0
