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commit 0130bd3d09666659e000f0457596b681511b79d0 Author: Jerzy Kasenberg <[email protected]> AuthorDate: Tue Sep 15 10:37:02 2026 +0200 mcu/stm32h5: Fix wait for PLL source clock Busy loop that waits for source oscillator to start is executed only if given PLL is to be enabled. Previously if PLL was not enabled and HSE was not enabled code would stack waiting for HSE to settle whene it was not enabled. --- hw/mcu/stm/stm32h5xx/src/clock_stm32h5xx.c | 27 ++++++++++++++++++--------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/hw/mcu/stm/stm32h5xx/src/clock_stm32h5xx.c b/hw/mcu/stm/stm32h5xx/src/clock_stm32h5xx.c index 33ced9a8f..828d5bf32 100644 --- a/hw/mcu/stm/stm32h5xx/src/clock_stm32h5xx.c +++ b/hw/mcu/stm/stm32h5xx/src/clock_stm32h5xx.c @@ -124,10 +124,13 @@ SystemClock_Config(void) LL_RCC_SetUSBClockSource(MYNEWT_VAL_STM32_CLOCK_USBSEL); } - BUSY_LOOP(PLL_VAL(PLL1, SOURCE) == LL_RCC_PLL1SOURCE_HSE && !LL_RCC_HSE_IsReady()); - BUSY_LOOP(PLL_VAL(PLL1, SOURCE) == LL_RCC_PLL1SOURCE_HSI && !LL_RCC_HSI_IsReady()); - BUSY_LOOP(PLL_VAL(PLL1, SOURCE) == LL_RCC_PLL1SOURCE_CSI && !LL_RCC_CSI_IsReady()); if (PLL_ON(PLL1)) { + BUSY_LOOP(PLL_VAL(PLL1, SOURCE) == LL_RCC_PLL1SOURCE_HSE && + !LL_RCC_HSE_IsReady()); + BUSY_LOOP(PLL_VAL(PLL1, SOURCE) == LL_RCC_PLL1SOURCE_HSI && + !LL_RCC_HSI_IsReady()); + BUSY_LOOP(PLL_VAL(PLL1, SOURCE) == LL_RCC_PLL1SOURCE_CSI && + !LL_RCC_CSI_IsReady()); LL_RCC_PLL1_SetSource(MYNEWT_VAL_STM32_CLOCK_PLL1_SOURCE); LL_RCC_PLL1_SetM(MYNEWT_VAL_STM32_CLOCK_PLL1_PLLM); LL_RCC_PLL1_SetN(MYNEWT_VAL_STM32_CLOCK_PLL1_PLLN); @@ -144,10 +147,13 @@ SystemClock_Config(void) LL_RCC_PLL1Q_Enable(); } - BUSY_LOOP(PLL_VAL(PLL2, SOURCE) == LL_RCC_PLL1SOURCE_HSE && !LL_RCC_HSE_IsReady()); - BUSY_LOOP(PLL_VAL(PLL2, SOURCE) == LL_RCC_PLL1SOURCE_HSI && !LL_RCC_HSI_IsReady()); - BUSY_LOOP(PLL_VAL(PLL2, SOURCE) == LL_RCC_PLL1SOURCE_CSI && !LL_RCC_CSI_IsReady()); if (PLL_ON(PLL2)) { + BUSY_LOOP(PLL_VAL(PLL2, SOURCE) == LL_RCC_PLL1SOURCE_HSE && + !LL_RCC_HSE_IsReady()); + BUSY_LOOP(PLL_VAL(PLL2, SOURCE) == LL_RCC_PLL1SOURCE_HSI && + !LL_RCC_HSI_IsReady()); + BUSY_LOOP(PLL_VAL(PLL2, SOURCE) == LL_RCC_PLL1SOURCE_CSI && + !LL_RCC_CSI_IsReady()); LL_RCC_PLL2_SetSource(MYNEWT_VAL_STM32_CLOCK_PLL2_SOURCE); LL_RCC_PLL2_SetM(MYNEWT_VAL_STM32_CLOCK_PLL2_PLLM); LL_RCC_PLL2_SetN(MYNEWT_VAL_STM32_CLOCK_PLL2_PLLN); @@ -165,10 +171,13 @@ SystemClock_Config(void) } #if RCC_CR_PLL3ON - BUSY_LOOP(PLL_VAL(PLL3, SOURCE) == LL_RCC_PLL1SOURCE_HSE && !LL_RCC_HSE_IsReady()); - BUSY_LOOP(PLL_VAL(PLL3, SOURCE) == LL_RCC_PLL1SOURCE_HSI && !LL_RCC_HSI_IsReady()); - BUSY_LOOP(PLL_VAL(PLL3, SOURCE) == LL_RCC_PLL1SOURCE_CSI && !LL_RCC_CSI_IsReady()); if (PLL_ON(PLL3)) { + BUSY_LOOP(PLL_VAL(PLL3, SOURCE) == LL_RCC_PLL1SOURCE_HSE && + !LL_RCC_HSE_IsReady()); + BUSY_LOOP(PLL_VAL(PLL3, SOURCE) == LL_RCC_PLL1SOURCE_HSI && + !LL_RCC_HSI_IsReady()); + BUSY_LOOP(PLL_VAL(PLL3, SOURCE) == LL_RCC_PLL1SOURCE_CSI && + !LL_RCC_CSI_IsReady()); LL_RCC_PLL3_SetSource(MYNEWT_VAL_STM32_CLOCK_PLL3_SOURCE); LL_RCC_PLL3_SetM(MYNEWT_VAL_STM32_CLOCK_PLL3_PLLM); LL_RCC_PLL3_SetN(MYNEWT_VAL_STM32_CLOCK_PLL3_PLLN);
