Gabriel39 commented on code in PR #9663:
URL: https://github.com/apache/incubator-doris/pull/9663#discussion_r877799221


##########
be/src/vec/exec/join/vhash_join_node.cpp:
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@@ -26,6 +26,8 @@
 #include "vec/exprs/vexpr_context.h"
 #include "vec/utils/util.hpp"
 
+#define PREFETCH_COUNT (size_t(32 * 1024) / CACHE_LINE_SIZE)

Review Comment:
   To achieve best performance, we should take more information about cache 
size.
   For example, l1d cache size is 64KB in AMD Epyc server processor[1] while 
48KB in Intel Icelake one[2]. 
   
   [1] https://www.club386.com/amd-unleashes-epyc-7003-series-with-3d-v-cache
   [2] 
https://www.techpowerup.com/248825/intel-increases-l1d-and-l2-cache-sizes-with-ice-lake



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