Author: ctopper
Date: Tue May 22 22:51:52 2018
New Revision: 333062
URL: http://llvm.org/viewvc/llvm-project?rev=333062&view=rev
Log:
[X86] In the floating point max reduction intrinsics, negate infinity before
feeding it to set1.
Previously we negated the whole vector after splatting infinity. But its better
to negate the infinity before splatting. This generates IR with the negate
already folded with the infinity constant.
Modified:
cfe/trunk/lib/Headers/avx512fintrin.h
cfe/trunk/test/CodeGen/avx512-reduceMinMaxIntrin.c
Modified: cfe/trunk/lib/Headers/avx512fintrin.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/avx512fintrin.h?rev=333062&r1=333061&r2=333062&view=diff
==============================================================================
--- cfe/trunk/lib/Headers/avx512fintrin.h (original)
+++ cfe/trunk/lib/Headers/avx512fintrin.h Tue May 22 22:51:52 2018
@@ -9956,7 +9956,7 @@ _mm512_mask_reduce_max_epu64(__mmask8 __
static __inline__ double __DEFAULT_FN_ATTRS
_mm512_mask_reduce_max_pd(__mmask8 __M, __m512d __V) {
- _mm512_mask_reduce_maxMin_64bit(__V, -_mm512_set1_pd(__builtin_inf()),
+ _mm512_mask_reduce_maxMin_64bit(__V, _mm512_set1_pd(-__builtin_inf()),
max_pd, d, f, pd, __M);
}
@@ -10099,7 +10099,7 @@ _mm512_mask_reduce_max_epu32(__mmask16 _
static __inline__ float __DEFAULT_FN_ATTRS
_mm512_mask_reduce_max_ps(__mmask16 __M, __m512 __V) {
- _mm512_mask_reduce_maxMin_32bit(__V,-_mm512_set1_ps(__builtin_inff()),
max_ps, , f,
+ _mm512_mask_reduce_maxMin_32bit(__V,_mm512_set1_ps(-__builtin_inff()),
max_ps, , f,
ps, __M);
}
Modified: cfe/trunk/test/CodeGen/avx512-reduceMinMaxIntrin.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/avx512-reduceMinMaxIntrin.c?rev=333062&r1=333061&r2=333062&view=diff
==============================================================================
--- cfe/trunk/test/CodeGen/avx512-reduceMinMaxIntrin.c (original)
+++ cfe/trunk/test/CodeGen/avx512-reduceMinMaxIntrin.c Tue May 22 22:51:52 2018
@@ -564,7 +564,7 @@ unsigned long test_mm512_mask_reduce_max
// CHECK: store <8 x double> [[TMP1]], <8 x double>* [[__V_ADDR_I]], align 64
// CHECK: [[TMP2:%.*]] = load i8, i8* [[__M_ADDR_I]], align 1
// CHECK: [[TMP3:%.*]] = load <8 x double>, <8 x double>* [[__V_ADDR_I]],
align 64
-// CHECK: store double 0x7FF0000000000000, double* [[__W_ADDR_I_I]], align 8
+// CHECK: store double 0xFFF0000000000000, double* [[__W_ADDR_I_I]], align 8
// CHECK: [[TMP4:%.*]] = load double, double* [[__W_ADDR_I_I]], align 8
// CHECK: [[VECINIT_I_I:%.*]] = insertelement <8 x double> undef, double
[[TMP4]], i32 0
// CHECK: [[TMP5:%.*]] = load double, double* [[__W_ADDR_I_I]], align 8
@@ -583,9 +583,8 @@ unsigned long test_mm512_mask_reduce_max
// CHECK: [[VECINIT7_I_I:%.*]] = insertelement <8 x double>
[[VECINIT6_I_I]], double [[TMP11]], i32 7
// CHECK: store <8 x double> [[VECINIT7_I_I]], <8 x double>*
[[_COMPOUNDLITERAL_I_I]], align 64
// CHECK: [[TMP12:%.*]] = load <8 x double>, <8 x double>*
[[_COMPOUNDLITERAL_I_I]], align 64
-// CHECK: [[SUB_I:%.*]] = fsub <8 x double> <double -0.000000e+00, double
-0.000000e+00, double -0.000000e+00, double -0.000000e+00, double
-0.000000e+00, double -0.000000e+00, double -0.000000e+00, double
-0.000000e+00>, [[TMP12]]
// CHECK: [[TMP13:%.*]] = bitcast i8 [[TMP2]] to <8 x i1>
-// CHECK: [[TMP14:%.*]] = select <8 x i1> [[TMP13]], <8 x double> [[TMP3]],
<8 x double> [[SUB_I]]
+// CHECK: [[TMP14:%.*]] = select <8 x i1> [[TMP13]], <8 x double> [[TMP3]],
<8 x double> [[TMP12]]
// CHECK: store <8 x double> [[TMP14]], <8 x double>* [[__V_ADDR_I]], align
64
// CHECK: [[TMP15:%.*]] = load <8 x double>, <8 x double>* [[__V_ADDR_I]],
align 64
// CHECK: [[TMP16:%.*]] = load <8 x double>, <8 x double>* [[__V_ADDR_I]],
align 64
@@ -1859,7 +1858,7 @@ unsigned int test_mm512_mask_reduce_max_
// CHECK: store <16 x float> [[TMP1]], <16 x float>* [[__V_ADDR_I]], align 64
// CHECK: [[TMP2:%.*]] = load i16, i16* [[__M_ADDR_I]], align 2
// CHECK: [[TMP3:%.*]] = load <16 x float>, <16 x float>* [[__V_ADDR_I]],
align 64
-// CHECK: store float 0x7FF0000000000000, float* [[__W_ADDR_I_I]], align 4
+// CHECK: store float 0xFFF0000000000000, float* [[__W_ADDR_I_I]], align 4
// CHECK: [[TMP4:%.*]] = load float, float* [[__W_ADDR_I_I]], align 4
// CHECK: [[VECINIT_I_I:%.*]] = insertelement <16 x float> undef, float
[[TMP4]], i32 0
// CHECK: [[TMP5:%.*]] = load float, float* [[__W_ADDR_I_I]], align 4
@@ -1894,9 +1893,8 @@ unsigned int test_mm512_mask_reduce_max_
// CHECK: [[VECINIT15_I_I:%.*]] = insertelement <16 x float>
[[VECINIT14_I_I]], float [[TMP19]], i32 15
// CHECK: store <16 x float> [[VECINIT15_I_I]], <16 x float>*
[[_COMPOUNDLITERAL_I_I]], align 64
// CHECK: [[TMP20:%.*]] = load <16 x float>, <16 x float>*
[[_COMPOUNDLITERAL_I_I]], align 64
-// CHECK: [[SUB_I:%.*]] = fsub <16 x float> <float -0.000000e+00, float
-0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00,
float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float
-0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00,
float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float
-0.000000e+00>, [[TMP20]]
// CHECK: [[TMP21:%.*]] = bitcast i16 [[TMP2]] to <16 x i1>
-// CHECK: [[TMP22:%.*]] = select <16 x i1> [[TMP21]], <16 x float> [[TMP3]],
<16 x float> [[SUB_I]]
+// CHECK: [[TMP22:%.*]] = select <16 x i1> [[TMP21]], <16 x float> [[TMP3]],
<16 x float> [[TMP20]]
// CHECK: store <16 x float> [[TMP22]], <16 x float>* [[__V_ADDR_I]], align
64
// CHECK: [[TMP23:%.*]] = load <16 x float>, <16 x float>* [[__V_ADDR_I]],
align 64
// CHECK: [[TMP24:%.*]] = load <16 x float>, <16 x float>* [[__V_ADDR_I]],
align 64
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