https://github.com/kmclaughlin-arm updated https://github.com/llvm/llvm-project/pull/226432
>From 772a8fc479bd138d119554009aac1d0d0f2cb877 Mon Sep 17 00:00:00 2001 From: Kerry McLaughlin <[email protected]> Date: Fri, 25 Sep 2026 09:59:45 +0000 Subject: [PATCH 1/2] [AArch64] Rename memory hints to avoid clash with arm_acle.h macros Renames the hints in AArch64MemoryHints.h, as HINT_STSHH_KEEP and HINT_STSHH_STRM are already defined in arm_acle.h. --- clang/lib/CodeGen/TargetBuiltins/ARM.cpp | 2 +- clang/lib/Sema/SemaARM.cpp | 2 +- llvm/include/llvm/Support/AArch64MemoryHints.h | 16 ++++++++-------- llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 6 +++--- 4 files changed, 13 insertions(+), 13 deletions(-) diff --git a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp index 52a7564789fb77..56e440a2aa66fe 100644 --- a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp @@ -2112,7 +2112,7 @@ static Value *EmitAtomicStoreWithHintBuiltin(CodeGenFunction &CGF, unsigned HintArg = Result.Val.getInt().getExtValue(); // Attach the hint if valid - if (toAArch64MemoryHint(HintArg) != AArch64MemoryHint::HINT_NONE) { + if (toAArch64MemoryHint(HintArg) != AArch64MemoryHint::MEM_HINT_NONE) { LLVMContext &Ctx = CGM.getLLVMContext(); MDNode *MemHint = MDNode::get( Ctx, {MDString::get(Ctx, "aarch64.mem_hint"), diff --git a/clang/lib/Sema/SemaARM.cpp b/clang/lib/Sema/SemaARM.cpp index 2bf6901bcc07f2..9c24245cfe5a12 100644 --- a/clang/lib/Sema/SemaARM.cpp +++ b/clang/lib/Sema/SemaARM.cpp @@ -434,7 +434,7 @@ bool SemaARM::BuiltinARMAtomicStoreHintCall(unsigned BuiltinID, << Hint->getType() << Hint->getSourceRange(); if (llvm::toAArch64MemoryHint(HintAP->getZExtValue()) == - llvm::AArch64MemoryHint::HINT_NONE) { + llvm::AArch64MemoryHint::MEM_HINT_NONE) { Diag(TheCall->getBeginLoc(), diag::warn_atomic_hint_has_invalid_hint_type) << *HintAP << Hint->getSourceRange(); return false; diff --git a/llvm/include/llvm/Support/AArch64MemoryHints.h b/llvm/include/llvm/Support/AArch64MemoryHints.h index 44ac64e481e80b..6c93fb95535738 100644 --- a/llvm/include/llvm/Support/AArch64MemoryHints.h +++ b/llvm/include/llvm/Support/AArch64MemoryHints.h @@ -11,24 +11,24 @@ namespace llvm { enum class AArch64MemoryHint { - HINT_NONE = 0, - HINT_STSHH_KEEP = 1, - HINT_STSHH_STRM = 2, + MEM_HINT_NONE = 0, + MEM_HINT_STSHH_KEEP = 1, + MEM_HINT_STSHH_STRM = 2, }; template <typename Int> inline bool isValidAArch64MemoryHintValue(Int I) { - return (Int)AArch64MemoryHint::HINT_STSHH_KEEP <= I && - I <= (Int)AArch64MemoryHint::HINT_STSHH_STRM; + return (Int)AArch64MemoryHint::MEM_HINT_STSHH_KEEP <= I && + I <= (Int)AArch64MemoryHint::MEM_HINT_STSHH_STRM; } template <typename Int> inline AArch64MemoryHint toAArch64MemoryHint(Int I) { switch (I) { case 0: - return AArch64MemoryHint::HINT_STSHH_KEEP; + return AArch64MemoryHint::MEM_HINT_STSHH_KEEP; case 1: - return AArch64MemoryHint::HINT_STSHH_STRM; + return AArch64MemoryHint::MEM_HINT_STSHH_STRM; default: - return AArch64MemoryHint::HINT_NONE; + return AArch64MemoryHint::MEM_HINT_NONE; } } } // namespace llvm diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index ee87070c127272..3694fa70841be3 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -4624,7 +4624,7 @@ AArch64DAGToDAGISel::decodeMemoryHintFlags(MachineMemOperand *MMO) const { int MemoryHint = -1; const MDNode *MemCacheHint = MMO->getMemCacheHint(); if (!MemCacheHint) - return AArch64MemoryHint::HINT_NONE; + return AArch64MemoryHint::MEM_HINT_NONE; for (unsigned I = 0; I + 1 < MemCacheHint->getNumOperands(); I += 2) { if (MemCacheHint->getOperand(I).equalsStr("aarch64.mem_hint")) { @@ -4639,12 +4639,12 @@ AArch64DAGToDAGISel::decodeMemoryHintFlags(MachineMemOperand *MMO) const { bool AArch64DAGToDAGISel::isAtomicSTSHH_KEEP(SDNode *N) const { return decodeMemoryHintFlags(cast<MemSDNode>(N)->getMemOperand()) == - AArch64MemoryHint::HINT_STSHH_KEEP; + AArch64MemoryHint::MEM_HINT_STSHH_KEEP; } bool AArch64DAGToDAGISel::isAtomicSTSHH_STRM(SDNode *N) const { return decodeMemoryHintFlags(cast<MemSDNode>(N)->getMemOperand()) == - AArch64MemoryHint::HINT_STSHH_STRM; + AArch64MemoryHint::MEM_HINT_STSHH_STRM; } bool AArch64DAGToDAGISel::SelectSVEAddSubImm(SDValue N, MVT VT, SDValue &Imm, >From 1ad4bab40f0cc908e093bfaa4969ba9633753948 Mon Sep 17 00:00:00 2001 From: Kerry McLaughlin <[email protected]> Date: Fri, 25 Sep 2026 12:47:40 +0000 Subject: [PATCH 2/2] - Change HINT_STSHH_KEEP/HINT_STSHH_STRM to const int in arm_acle.h --- clang/lib/CodeGen/TargetBuiltins/ARM.cpp | 2 +- clang/lib/Headers/arm_acle.h | 6 ++++-- clang/lib/Sema/SemaARM.cpp | 10 +++++----- llvm/include/llvm/Support/AArch64MemoryHints.h | 16 ++++++++-------- llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 6 +++--- 5 files changed, 21 insertions(+), 19 deletions(-) diff --git a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp index 56e440a2aa66fe..e20fa60ee132bc 100644 --- a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp @@ -2112,7 +2112,7 @@ static Value *EmitAtomicStoreWithHintBuiltin(CodeGenFunction &CGF, unsigned HintArg = Result.Val.getInt().getExtValue(); // Attach the hint if valid - if (toAArch64MemoryHint(HintArg) != AArch64MemoryHint::MEM_HINT_NONE) { + if (toAArch64MemoryHint(HintArg) != AArch64MemoryHint::NONE) { LLVMContext &Ctx = CGM.getLLVMContext(); MDNode *MemHint = MDNode::get( Ctx, {MDString::get(Ctx, "aarch64.mem_hint"), diff --git a/clang/lib/Headers/arm_acle.h b/clang/lib/Headers/arm_acle.h index 715fe851b0c322..d24eeac7575151 100644 --- a/clang/lib/Headers/arm_acle.h +++ b/clang/lib/Headers/arm_acle.h @@ -40,6 +40,10 @@ void __sev(void); void __sevl(void); void __yield(void); +/* Atomic Hints */ +const int HINT_STSHH_KEEP = 0; +const int HINT_STSHH_STRM = 1; + #if defined(__ARM_32BIT_STATE) && __ARM_32BIT_STATE #define __dbg(t) __builtin_arm_dbg(t) #endif @@ -744,8 +748,6 @@ __arm_st64bv0(void *__addr, data512_t __value) { /* Atomic store with hints */ #if defined(__ARM_64BIT_STATE) && __ARM_64BIT_STATE -#define HINT_STSHH_KEEP 0 -#define HINT_STSHH_STRM 1 #define __arm_atomic_store_with_hint(ptr, data, memory_order, hint) \ __builtin_arm_atomic_store_with_hint(ptr, data, memory_order, hint) #endif diff --git a/clang/lib/Sema/SemaARM.cpp b/clang/lib/Sema/SemaARM.cpp index 9c24245cfe5a12..b4a04910603f07 100644 --- a/clang/lib/Sema/SemaARM.cpp +++ b/clang/lib/Sema/SemaARM.cpp @@ -427,16 +427,16 @@ bool SemaARM::BuiltinARMAtomicStoreHintCall(unsigned BuiltinID, TheCall->setArg(3, Hint); if (!Hint->isValueDependent()) { - std::optional<llvm::APSInt> HintAP = Hint->getIntegerConstantExpr(Context); - if (!HintAP) + Expr::EvalResult HintResult; + if (!Hint->EvaluateAsInt(HintResult, Context)) return Diag(TheCall->getBeginLoc(), diag::err_atomic_hint_has_invalid_hint_type) << Hint->getType() << Hint->getSourceRange(); - if (llvm::toAArch64MemoryHint(HintAP->getZExtValue()) == - llvm::AArch64MemoryHint::MEM_HINT_NONE) { + unsigned HintVal = HintResult.Val.getInt().getZExtValue(); + if (llvm::toAArch64MemoryHint(HintVal) == llvm::AArch64MemoryHint::NONE) { Diag(TheCall->getBeginLoc(), diag::warn_atomic_hint_has_invalid_hint_type) - << *HintAP << Hint->getSourceRange(); + << HintVal << Hint->getSourceRange(); return false; } } diff --git a/llvm/include/llvm/Support/AArch64MemoryHints.h b/llvm/include/llvm/Support/AArch64MemoryHints.h index 6c93fb95535738..b917191499cac1 100644 --- a/llvm/include/llvm/Support/AArch64MemoryHints.h +++ b/llvm/include/llvm/Support/AArch64MemoryHints.h @@ -11,24 +11,24 @@ namespace llvm { enum class AArch64MemoryHint { - MEM_HINT_NONE = 0, - MEM_HINT_STSHH_KEEP = 1, - MEM_HINT_STSHH_STRM = 2, + NONE = 0, + STSHH_KEEP = 1, + STSHH_STRM = 2, }; template <typename Int> inline bool isValidAArch64MemoryHintValue(Int I) { - return (Int)AArch64MemoryHint::MEM_HINT_STSHH_KEEP <= I && - I <= (Int)AArch64MemoryHint::MEM_HINT_STSHH_STRM; + return (Int)AArch64MemoryHint::STSHH_KEEP <= I && + I <= (Int)AArch64MemoryHint::STSHH_STRM; } template <typename Int> inline AArch64MemoryHint toAArch64MemoryHint(Int I) { switch (I) { case 0: - return AArch64MemoryHint::MEM_HINT_STSHH_KEEP; + return AArch64MemoryHint::STSHH_KEEP; case 1: - return AArch64MemoryHint::MEM_HINT_STSHH_STRM; + return AArch64MemoryHint::STSHH_STRM; default: - return AArch64MemoryHint::MEM_HINT_NONE; + return AArch64MemoryHint::NONE; } } } // namespace llvm diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp index 3694fa70841be3..48c0e37151b9c4 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp @@ -4624,7 +4624,7 @@ AArch64DAGToDAGISel::decodeMemoryHintFlags(MachineMemOperand *MMO) const { int MemoryHint = -1; const MDNode *MemCacheHint = MMO->getMemCacheHint(); if (!MemCacheHint) - return AArch64MemoryHint::MEM_HINT_NONE; + return AArch64MemoryHint::NONE; for (unsigned I = 0; I + 1 < MemCacheHint->getNumOperands(); I += 2) { if (MemCacheHint->getOperand(I).equalsStr("aarch64.mem_hint")) { @@ -4639,12 +4639,12 @@ AArch64DAGToDAGISel::decodeMemoryHintFlags(MachineMemOperand *MMO) const { bool AArch64DAGToDAGISel::isAtomicSTSHH_KEEP(SDNode *N) const { return decodeMemoryHintFlags(cast<MemSDNode>(N)->getMemOperand()) == - AArch64MemoryHint::MEM_HINT_STSHH_KEEP; + AArch64MemoryHint::STSHH_KEEP; } bool AArch64DAGToDAGISel::isAtomicSTSHH_STRM(SDNode *N) const { return decodeMemoryHintFlags(cast<MemSDNode>(N)->getMemOperand()) == - AArch64MemoryHint::MEM_HINT_STSHH_STRM; + AArch64MemoryHint::STSHH_STRM; } bool AArch64DAGToDAGISel::SelectSVEAddSubImm(SDValue N, MVT VT, SDValue &Imm, _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
