https://github.com/ChunyuLiao updated https://github.com/llvm/llvm-project/pull/217199
>From f87aa9ed9e871ddd4a29276d4860fc679f7dfa6d Mon Sep 17 00:00:00 2001 From: Liao Chunyu <[email protected]> Date: Tue, 18 Aug 2026 04:20:53 +0000 Subject: [PATCH 1/4] [RISCV]Add RVA23.1 and RVB23.1 experimental profiles RVA23.1 state: https://riscv.atlassian.net/browse/RVS-4180 RVB23.1 state: https://riscv.atlassian.net/browse/RVS-4184 --- .../Driver/print-supported-extensions-riscv.c | 2 ++ clang/test/Driver/riscv-profiles.c | 24 +++++++++++++++++++ llvm/docs/RISCVUsage.md | 2 ++ llvm/lib/Target/RISCV/RISCVProfiles.td | 16 +++++++++++++ llvm/test/CodeGen/RISCV/attributes.ll | 4 ++++ llvm/test/CodeGen/RISCV/features-info.ll | 2 ++ .../TargetParser/RISCVISAInfoTest.cpp | 8 +++++++ 7 files changed, 58 insertions(+) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index f90a5fc581baa..9efb704a1accc 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -295,6 +295,8 @@ // CHECK-NEXT: rvi20u64 // CHECK-EMPTY: // CHECK-NEXT: Experimental Profiles +// CHECK-NEXT: rva23p1s64 +// CHECK-NEXT: rvb23p1s64 // CHECK-NEXT: rvm23u32 // CHECK-EMPTY: // CHECK-NEXT: Use -march to specify the target's extension. diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c index 9639c03bdbe26..1aff05496b498 100644 --- a/clang/test/Driver/riscv-profiles.c +++ b/clang/test/Driver/riscv-profiles.c @@ -154,6 +154,14 @@ // RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23s64 \ // RUN: | FileCheck -check-prefix=RVA23S64 %s +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23p1s64 -menable-experimental-extensions \ +// RUN: | FileCheck -check-prefix=RVA23P1S64 %s +// RVA23P1S64: "-target-feature" "+ssccfg" +// RVA23P1S64: "-target-feature" "+sscsrind" +// RVA23P1S64: "-target-feature" "+ssctr" +// RVA23P1S64: "-target-feature" "+ssdbltrp" +// RVA23P1S64: "-target-feature" "+ssqosid" +// RVA23P1S64: "-target-feature" "+svrsw60t59b" // RVA23S64: "-target-feature" "+m" // RVA23S64: "-target-feature" "+a" // RVA23S64: "-target-feature" "+f" @@ -249,6 +257,14 @@ // RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23s64 \ // RUN: | FileCheck -check-prefix=RVB23S64 %s +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23p1s64 -menable-experimental-extensions \ +// RUN: | FileCheck -check-prefix=RVB23P1S64 %s +// RVB23P1S64: "-target-feature" "+ssccfg" +// RVB23P1S64: "-target-feature" "+sscsrind" +// RVB23P1S64: "-target-feature" "+ssctr" +// RVB23P1S64: "-target-feature" "+ssdbltrp" +// RVB23P1S64: "-target-feature" "+ssqosid" +// RVB23P1S64: "-target-feature" "+svrsw60t59b" // RVB23S64: "-target-feature" "+m" // RVB23S64: "-target-feature" "+a" // RVB23S64: "-target-feature" "+f" @@ -334,6 +350,14 @@ // RUN: not %clang --target=riscv64 -### -c %s 2>&1 -march=rva22u64zfa | FileCheck -check-prefix=INVALID-ADDITIONAL %s // INVALID-ADDITIONAL: error: invalid arch name 'rva22u64zfa', additional extensions must be after separator '_' +// RUN: not %clang --target=riscv64 -### -c %s 2>&1 -march=rva23p1s64 | FileCheck -check-prefix=RVA23P1-EXPERIMENTAL-NOFLAG %s +// RVA23P1-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rva23p1s64' +// RVA23P1-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions' for profile 'rva23p1s64' + +// RUN: not %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23p1s64 | FileCheck -check-prefix=RVB23P1-EXPERIMENTAL-NOFLAG %s +// RVB23P1-EXPERIMENTAL-NOFLAG: error: invalid arch name 'rvb23p1s64' +// RVB23P1-EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions' for profile 'rvb23p1s64' + // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -march=rvm23u32 | FileCheck -check-prefix=EXPERIMENTAL-NOFLAG %s // EXPERIMENTAL-NOFLAG: error: invalid arch name 'rvm23u32' // EXPERIMENTAL-NOFLAG: requires '-menable-experimental-extensions' for profile 'rvm23u32' diff --git a/llvm/docs/RISCVUsage.md b/llvm/docs/RISCVUsage.md index 54974f1c90a28..a284d2a9c6e67 100644 --- a/llvm/docs/RISCVUsage.md +++ b/llvm/docs/RISCVUsage.md @@ -83,6 +83,8 @@ Profiles that are not yet ratified cannot be used unless `-menable-experimental-extensions` (or equivalent for other tools) is specified. This applies to the following profiles: +- `rva23p1s64` +- `rvb23p1s64` - `rvm23u32` (riscv-extensions)= diff --git a/llvm/lib/Target/RISCV/RISCVProfiles.td b/llvm/lib/Target/RISCV/RISCVProfiles.td index 92389fecd0b1d..ca0414af900fb 100644 --- a/llvm/lib/Target/RISCV/RISCVProfiles.td +++ b/llvm/lib/Target/RISCV/RISCVProfiles.td @@ -85,6 +85,13 @@ defvar RVA23S64BaseFeatures = !listconcat(RVA22S64BaseFeatures, defvar RVA23S64Features = !listconcat(RVA23U64Features, RVA23S64BaseFeatures); +defvar RVA23P1S64Features = !listconcat(RVA23S64Features, + [FeatureStdExtSvrsw60t59b, + FeatureStdExtSsdbltrp, + FeatureStdExtSsccfg, + FeatureStdExtSsctr, + FeatureStdExtSsqosid]); + // RVB Profile Family defvar RVB23U64Features = !listconcat(RVA20U64BaseFeatures, @@ -120,6 +127,13 @@ defvar RVB23S64Features = !listconcat(RVB23U64Features, FeatureStdExtSscofpmf, FeatureStdExtSsu64xl]); +defvar RVB23P1S64Features = !listconcat(RVB23S64Features, + [FeatureStdExtSvrsw60t59b, + FeatureStdExtSsdbltrp, + FeatureStdExtSsccfg, + FeatureStdExtSsctr, + FeatureStdExtSsqosid]); + // RVM Profile Family defvar RVM23U32Features = [Feature32Bit, @@ -160,4 +174,6 @@ def RVA23U64 : RISCVProfile<"rva23u64", RVA23U64Features>; def RVA23S64 : RISCVProfile<"rva23s64", RVA23S64Features>; def RVB23U64 : RISCVProfile<"rvb23u64", RVB23U64Features>; def RVB23S64 : RISCVProfile<"rvb23s64", RVB23S64Features>; +def RVA23P1S64 : RISCVExperimentalProfile<"rva23p1s64", RVA23P1S64Features>; +def RVB23P1S64 : RISCVExperimentalProfile<"rvb23p1s64", RVB23P1S64Features>; def RVM23U32 : RISCVExperimentalProfile<"rvm23u32", RVM23U32Features>; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index df521014e3d16..562a8b9edcf70 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -352,6 +352,8 @@ ; RUN: llc -mtriple=riscv64 -mattr=+rva23s64 %s -o - | FileCheck --check-prefix=RVA23S64 %s ; RUN: llc -mtriple=riscv64 -mattr=+rvb23u64 %s -o - | FileCheck --check-prefix=RVB23U64 %s ; RUN: llc -mtriple=riscv64 -mattr=+rvb23s64 %s -o - | FileCheck --check-prefix=RVB23S64 %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-rva23p1s64 %s -o - | FileCheck --check-prefix=RVA23P1S64 %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-rvb23p1s64 %s -o - | FileCheck --check-prefix=RVB23P1S64 %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-rvm23u32 %s -o - | FileCheck --check-prefix=RVM23U32 %s ; CHECK: .attribute 4, 16 @@ -703,6 +705,8 @@ ; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" ; RVB23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0" ; RVB23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" +; RVA23P1S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccfg1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sscsrind1p0_ssctr1p0_ssdbltrp1p0_ssnpm1p0_ssqosid1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0_svrsw60t59b1p0" +; RVB23P1S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccfg1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sscsrind1p0_ssctr1p0_ssdbltrp1p0_ssqosid1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0_svrsw60t59b1p0" ; RVM23U32: .attribute 5, "rv32i2p1_m2p0_c2p0_b1p0_zicbop1p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zimop1p0_zmmul1p0_zca1p0_zcb1p0_zce1p0_zcmop1p0_zcmp1p0_zcmt1p0_zba1p0_zbb1p0_zbs1p0" define i32 @addi(i32 %a) { diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 08cf62f61296c..7142ab5472d9c 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -23,6 +23,8 @@ ; CHECK-NEXT: exact-asm - Enable Exact Assembly (Disables Compression and Relaxation). ; CHECK-NEXT: experimental - Experimental intrinsics. ; CHECK-NEXT: experimental-p - 'P' ('Base P' (Packed SIMD)). +; CHECK-NEXT: experimental-rva23p1s64 - RISC-V experimental-rva23p1s64 profile. +; CHECK-NEXT: experimental-rvb23p1s64 - RISC-V experimental-rvb23p1s64 profile. ; CHECK-NEXT: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile. ; CHECK-NEXT: experimental-smcsps - 'Smcsps' (Conditional Stack Pointer Swap at Machine Level). ; CHECK-NEXT: experimental-smehv - 'Smehv' (Synchronous Exception Hardware Vectoring at Machine Level). diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 94261564e8043..de50dbd78552c 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -924,6 +924,12 @@ TEST(ParseArchString, TEST(ParseArchString, RejectsExperimentalProfilesIfEnableExperimentalExtensionsNotSet) { + EXPECT_EQ( + toString(RISCVISAInfo::parseArchString("rva23p1s64", false).takeError()), + "requires '-menable-experimental-extensions' for profile 'rva23p1s64'"); + EXPECT_EQ( + toString(RISCVISAInfo::parseArchString("rvb23p1s64", false).takeError()), + "requires '-menable-experimental-extensions' for profile 'rvb23p1s64'"); EXPECT_EQ( toString(RISCVISAInfo::parseArchString("rvm23u32", false).takeError()), "requires '-menable-experimental-extensions' for profile 'rvm23u32'"); @@ -1685,6 +1691,8 @@ Supported Profiles rvi20u64 Experimental Profiles + rva23p1s64 + rvb23p1s64 rvm23u32 Use -march to specify the target's extension. >From 42b4a1e22c4a163469dd6111da7a45f7fc59e121 Mon Sep 17 00:00:00 2001 From: Liao Chunyu <[email protected]> Date: Tue, 15 Sep 2026 11:42:54 +0800 Subject: [PATCH 2/4] Update llvm/lib/Target/RISCV/RISCVProfiles.td Co-authored-by: Pengcheng Wang <[email protected]> --- llvm/lib/Target/RISCV/RISCVProfiles.td | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVProfiles.td b/llvm/lib/Target/RISCV/RISCVProfiles.td index ca0414af900fb..83b5e6815c8ad 100644 --- a/llvm/lib/Target/RISCV/RISCVProfiles.td +++ b/llvm/lib/Target/RISCV/RISCVProfiles.td @@ -175,5 +175,6 @@ def RVA23S64 : RISCVProfile<"rva23s64", RVA23S64Features>; def RVB23U64 : RISCVProfile<"rvb23u64", RVB23U64Features>; def RVB23S64 : RISCVProfile<"rvb23s64", RVB23S64Features>; def RVA23P1S64 : RISCVExperimentalProfile<"rva23p1s64", RVA23P1S64Features>; -def RVB23P1S64 : RISCVExperimentalProfile<"rvb23p1s64", RVB23P1S64Features>; +def RVA23P1S64 : RISCVExperimentalProfile<"rva23p1s64", RVA23S64Features>; +def RVB23P1S64 : RISCVExperimentalProfile<"rvb23p1s64", RVB23S64Features>; def RVM23U32 : RISCVExperimentalProfile<"rvm23u32", RVM23U32Features>; >From 8abfb02110cd6e02ddcde89098641705fda30d3c Mon Sep 17 00:00:00 2001 From: Liao Chunyu <[email protected]> Date: Tue, 15 Sep 2026 04:09:28 +0000 Subject: [PATCH 3/4] Update testcases. --- clang/test/Driver/riscv-profiles.c | 29 +++++++++++++------------- llvm/docs/RISCVUsage.md | 5 +++++ llvm/lib/Target/RISCV/RISCVProfiles.td | 15 ------------- llvm/test/CodeGen/RISCV/attributes.ll | 10 +++++---- 4 files changed, 26 insertions(+), 33 deletions(-) diff --git a/clang/test/Driver/riscv-profiles.c b/clang/test/Driver/riscv-profiles.c index 1aff05496b498..63b347dd97ba8 100644 --- a/clang/test/Driver/riscv-profiles.c +++ b/clang/test/Driver/riscv-profiles.c @@ -155,13 +155,7 @@ // RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23s64 \ // RUN: | FileCheck -check-prefix=RVA23S64 %s // RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rva23p1s64 -menable-experimental-extensions \ -// RUN: | FileCheck -check-prefix=RVA23P1S64 %s -// RVA23P1S64: "-target-feature" "+ssccfg" -// RVA23P1S64: "-target-feature" "+sscsrind" -// RVA23P1S64: "-target-feature" "+ssctr" -// RVA23P1S64: "-target-feature" "+ssdbltrp" -// RVA23P1S64: "-target-feature" "+ssqosid" -// RVA23P1S64: "-target-feature" "+svrsw60t59b" +// RUN: | FileCheck -check-prefix=RVA23S64 %s // RVA23S64: "-target-feature" "+m" // RVA23S64: "-target-feature" "+a" // RVA23S64: "-target-feature" "+f" @@ -258,13 +252,7 @@ // RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23s64 \ // RUN: | FileCheck -check-prefix=RVB23S64 %s // RUN: %clang --target=riscv64 -### -c %s 2>&1 -march=rvb23p1s64 -menable-experimental-extensions \ -// RUN: | FileCheck -check-prefix=RVB23P1S64 %s -// RVB23P1S64: "-target-feature" "+ssccfg" -// RVB23P1S64: "-target-feature" "+sscsrind" -// RVB23P1S64: "-target-feature" "+ssctr" -// RVB23P1S64: "-target-feature" "+ssdbltrp" -// RVB23P1S64: "-target-feature" "+ssqosid" -// RVB23P1S64: "-target-feature" "+svrsw60t59b" +// RUN: | FileCheck -check-prefix=RVB23S64 %s // RVB23S64: "-target-feature" "+m" // RVB23S64: "-target-feature" "+a" // RVB23S64: "-target-feature" "+f" @@ -309,6 +297,19 @@ // RVB23S64: "-target-feature" "+svnapot" // RVB23S64: "-target-feature" "+svpbmt" +// RUN: %clang --target=riscv64 -### -c %s 2>&1 \ +// RUN: -march=rva23p1s64_ssccfg_ssctr_ssdbltrp_ssqosid_svrsw60t59b -menable-experimental-extensions \ +// RUN: | FileCheck -check-prefix=PROFILE-P1-OPTIONS %s +// RUN: %clang --target=riscv64 -### -c %s 2>&1 \ +// RUN: -march=rvb23p1s64_ssccfg_ssctr_ssdbltrp_ssqosid_svrsw60t59b -menable-experimental-extensions \ +// RUN: | FileCheck -check-prefix=PROFILE-P1-OPTIONS %s +// PROFILE-P1-OPTIONS: "-target-feature" "+ssccfg" +// PROFILE-P1-OPTIONS: "-target-feature" "+sscsrind" +// PROFILE-P1-OPTIONS: "-target-feature" "+ssctr" +// PROFILE-P1-OPTIONS: "-target-feature" "+ssdbltrp" +// PROFILE-P1-OPTIONS: "-target-feature" "+ssqosid" +// PROFILE-P1-OPTIONS: "-target-feature" "+svrsw60t59b" + // RUN: %clang --target=riscv32 -### -c %s 2>&1 -march=rvm23u32 -menable-experimental-extensions \ // RUN: | FileCheck -check-prefix=RVM23U32 %s // RVM23U32: "-target-feature" "+m" diff --git a/llvm/docs/RISCVUsage.md b/llvm/docs/RISCVUsage.md index a284d2a9c6e67..f409d72022b7c 100644 --- a/llvm/docs/RISCVUsage.md +++ b/llvm/docs/RISCVUsage.md @@ -87,6 +87,11 @@ specified. This applies to the following profiles: - `rvb23p1s64` - `rvm23u32` +The `rva23p1s64` and `rvb23p1s64` profiles enable the same mandatory extensions +as `rva23s64` and `rvb23s64`, respectively. Their additional optional extensions +must be requested explicitly, for example +`-march=rva23p1s64_ssctr -menable-experimental-extensions`. + (riscv-extensions)= ## Extensions diff --git a/llvm/lib/Target/RISCV/RISCVProfiles.td b/llvm/lib/Target/RISCV/RISCVProfiles.td index 83b5e6815c8ad..374ead904fe9b 100644 --- a/llvm/lib/Target/RISCV/RISCVProfiles.td +++ b/llvm/lib/Target/RISCV/RISCVProfiles.td @@ -85,13 +85,6 @@ defvar RVA23S64BaseFeatures = !listconcat(RVA22S64BaseFeatures, defvar RVA23S64Features = !listconcat(RVA23U64Features, RVA23S64BaseFeatures); -defvar RVA23P1S64Features = !listconcat(RVA23S64Features, - [FeatureStdExtSvrsw60t59b, - FeatureStdExtSsdbltrp, - FeatureStdExtSsccfg, - FeatureStdExtSsctr, - FeatureStdExtSsqosid]); - // RVB Profile Family defvar RVB23U64Features = !listconcat(RVA20U64BaseFeatures, @@ -127,13 +120,6 @@ defvar RVB23S64Features = !listconcat(RVB23U64Features, FeatureStdExtSscofpmf, FeatureStdExtSsu64xl]); -defvar RVB23P1S64Features = !listconcat(RVB23S64Features, - [FeatureStdExtSvrsw60t59b, - FeatureStdExtSsdbltrp, - FeatureStdExtSsccfg, - FeatureStdExtSsctr, - FeatureStdExtSsqosid]); - // RVM Profile Family defvar RVM23U32Features = [Feature32Bit, @@ -174,7 +160,6 @@ def RVA23U64 : RISCVProfile<"rva23u64", RVA23U64Features>; def RVA23S64 : RISCVProfile<"rva23s64", RVA23S64Features>; def RVB23U64 : RISCVProfile<"rvb23u64", RVB23U64Features>; def RVB23S64 : RISCVProfile<"rvb23s64", RVB23S64Features>; -def RVA23P1S64 : RISCVExperimentalProfile<"rva23p1s64", RVA23P1S64Features>; def RVA23P1S64 : RISCVExperimentalProfile<"rva23p1s64", RVA23S64Features>; def RVB23P1S64 : RISCVExperimentalProfile<"rvb23p1s64", RVB23S64Features>; def RVM23U32 : RISCVExperimentalProfile<"rvm23u32", RVM23U32Features>; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 562a8b9edcf70..917b045078d60 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -352,8 +352,10 @@ ; RUN: llc -mtriple=riscv64 -mattr=+rva23s64 %s -o - | FileCheck --check-prefix=RVA23S64 %s ; RUN: llc -mtriple=riscv64 -mattr=+rvb23u64 %s -o - | FileCheck --check-prefix=RVB23U64 %s ; RUN: llc -mtriple=riscv64 -mattr=+rvb23s64 %s -o - | FileCheck --check-prefix=RVB23S64 %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-rva23p1s64 %s -o - | FileCheck --check-prefix=RVA23P1S64 %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-rvb23p1s64 %s -o - | FileCheck --check-prefix=RVB23P1S64 %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-rva23p1s64 %s -o - | FileCheck --check-prefix=RVA23S64 %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-rvb23p1s64 %s -o - | FileCheck --check-prefix=RVB23S64 %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-rva23p1s64,+ssccfg,+ssctr,+ssdbltrp,+ssqosid,+svrsw60t59b %s -o - | FileCheck --check-prefix=RVA23P1S64-OPTIONS %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-rvb23p1s64,+ssccfg,+ssctr,+ssdbltrp,+ssqosid,+svrsw60t59b %s -o - | FileCheck --check-prefix=RVB23P1S64-OPTIONS %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-rvm23u32 %s -o - | FileCheck --check-prefix=RVM23U32 %s ; CHECK: .attribute 4, 16 @@ -705,8 +707,8 @@ ; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" ; RVB23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0" ; RVB23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" -; RVA23P1S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccfg1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sscsrind1p0_ssctr1p0_ssdbltrp1p0_ssnpm1p0_ssqosid1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0_svrsw60t59b1p0" -; RVB23P1S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccfg1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sscsrind1p0_ssctr1p0_ssdbltrp1p0_ssqosid1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0_svrsw60t59b1p0" +; RVA23P1S64-OPTIONS: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccfg1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sscsrind1p0_ssctr1p0_ssdbltrp1p0_ssnpm1p0_ssqosid1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0_svrsw60t59b1p0" +; RVB23P1S64-OPTIONS: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccfg1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sscsrind1p0_ssctr1p0_ssdbltrp1p0_ssqosid1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0_svrsw60t59b1p0" ; RVM23U32: .attribute 5, "rv32i2p1_m2p0_c2p0_b1p0_zicbop1p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zimop1p0_zmmul1p0_zca1p0_zcb1p0_zce1p0_zcmop1p0_zcmp1p0_zcmt1p0_zba1p0_zbb1p0_zbs1p0" define i32 @addi(i32 %a) { >From c20039f748d0693de02bbef64f2ffba2fd559061 Mon Sep 17 00:00:00 2001 From: Liao Chunyu <[email protected]> Date: Tue, 15 Sep 2026 06:06:07 +0000 Subject: [PATCH 4/4] ReleaseNotes --- llvm/docs/ReleaseNotes.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 2468c7ed01000..5fe4cefbf8a81 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -120,6 +120,8 @@ Makes programs 10x faster by doing Special New Thing. * Bump Svukte extension to 1.0. +* Added the experimental `RVA23P1S64` and `RVB23P1S64` profiles. + ### Changes to the WebAssembly Backend ### Changes to the Windows Target _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
