================
@@ -5452,6 +5452,323 @@ uint32_t test_vcvtad_u32_f64(float64_t a) {
return (uint32_t)vcvtad_u32_f64(a);
}
+//===------------------------------------------------------===//
+// 2.1.4.1 Convearions (int to float)
+// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#conversions
+//===------------------------------------------------------===//
+// LLVM-LABEL: @test_vcvt_f32_s32(
+// CIR-LABEL: @vcvt_f32_s32(
+float32x2_t test_vcvt_f32_s32(int32x2_t a) {
+// CIR: cir.cast int_to_float
+
+// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
+// LLVM: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
+// LLVM: [[VCVT_I:%.*]] = sitofp <2 x i32> [[TMP1]] to <2 x float>
+// LLVM: ret <2 x float> [[VCVT_I]]
+ return vcvt_f32_s32(a);
+}
+
+// LLVM-LABEL: @test_vcvtq_f32_s32(
+// CIR-LABEL: @vcvtq_f32_s32(
+float32x4_t test_vcvtq_f32_s32(int32x4_t a) {
+// CIR: cir.cast int_to_float
+
+// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
+// LLVM: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
+// LLVM: [[VCVT_I:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x float>
+// LLVM: ret <4 x float> [[VCVT_I]]
+ return vcvtq_f32_s32(a);
+}
+
+// LLVM-LABEL: @test_vcvt_f32_u32(
+// CIR-LABEL: @vcvt_f32_u32(
+float32x2_t test_vcvt_f32_u32(uint32x2_t a) {
+// CIR: cir.cast int_to_float
+
+// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]]) #[[ATTR0]] {
+// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8>
+// LLVM: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
+// LLVM: [[VCVT_I:%.*]] = uitofp <2 x i32> [[TMP1]] to <2 x float>
+// LLVM: ret <2 x float> [[VCVT_I]]
+ return vcvt_f32_u32(a);
+}
+
+// LLVM-LABEL: @test_vcvtq_f32_u32(
+// CIR-LABEL: @vcvtq_f32_u32(
+float32x4_t test_vcvtq_f32_u32(uint32x4_t a) {
+// CIR: cir.cast int_to_float
+
+// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]]) #[[ATTR0]] {
+// LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8>
+// LLVM: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
+// LLVM: [[VCVT_I:%.*]] = uitofp <4 x i32> [[TMP1]] to <4 x float>
+// LLVM: ret <4 x float> [[VCVT_I]]
+ return vcvtq_f32_u32(a);
+}
+
+// LLVM-LABEL: @test_vcvts_f32_s32(
+// CIR-LABEL: @vcvts_f32_s32(
+float32_t test_vcvts_f32_s32(int32_t a) {
+// CIR: cir.cast int_to_float
+
+// LLVM-SAME: i32 {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = sitofp i32 [[A]] to float
+// LLVM: ret float [[TMP0]]
+ return vcvts_f32_s32(a);
+}
+
+// LLVM-LABEL: @test_vcvts_f32_u32(
+// CIR-LABEL: @vcvts_f32_u32(
+float32_t test_vcvts_f32_u32(uint32_t a) {
+// CIR: cir.cast int_to_float
+
+// LLVM-SAME: i32 {{.*}} [[A:%.*]]) #[[ATTR0]] {
+// LLVM: [[TMP0:%.*]] = uitofp i32 [[A]] to float
+// LLVM: ret float [[TMP0]]
+ return vcvts_f32_u32(a);
+}
+
+// LLVM-LABEL: @test_vcvt_f64_s64(
+// CIR-LABEL: @vcvt_f64_s64(
+float64x1_t test_vcvt_f64_s64(int64x1_t a) {
+// CIR: cir.cast int_to_float
+
+// LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]]) #[[ATTR0]] {
+// LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>
+// LLVM: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
+// LLVM: [[VCVT_I:%.*]] = sitofp <1 x i64> [[TMP1]] to <1 x double>
+// LLVM: ret <1 x double> [[VCVT_I]]
+ return vcvt_f64_s64(a);
+}
+
+// LLVM-LABEL: @test_vcvtq_f64_s64(
+// CIR-LABEL: @vcvtq_f64_s64(
+float64x2_t test_vcvtq_f64_s64(int64x2_t a) {
+// CIR: cir.cast int_to_float
+
+// LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]]) #[[ATTR0]] {
+// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
+// LLVM: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
+// LLVM: [[VCVT_I:%.*]] = sitofp <2 x i64> [[TMP1]] to <2 x double>
+// LLVM: ret <2 x double> [[VCVT_I]]
+ return vcvtq_f64_s64(a);
+}
+
+// LLVM-LABEL: @test_vcvt_f64_u64(
+// CIR-LABEL: @vcvt_f64_u64(
+float64x1_t test_vcvt_f64_u64(uint64x1_t a) {
+// CIR: cir.cast int_to_float
+
+// LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]]) #[[ATTR0]] {
+// LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8>
+// LLVM: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
+// LLVM: [[VCVT_I:%.*]] = uitofp <1 x i64> [[TMP1]] to <1 x double>
+// LLVM: ret <1 x double> [[VCVT_I]]
+ return vcvt_f64_u64(a);
+}
+
+// LLVM-LABEL: @test_vcvtq_f64_u64(
+// CIR-LABEL: @vcvtq_f64_u64(
+float64x2_t test_vcvtq_f64_u64(uint64x2_t a) {
+// CIR: cir.cast int_to_float
+
+// LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]]) #[[ATTR0]] {
+// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8>
+// LLVM: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
+// LLVM: [[VCVT_I:%.*]] = uitofp <2 x i64> [[TMP1]] to <2 x double>
+// LLVM: ret <2 x double> [[VCVT_I]]
+ return vcvtq_f64_u64(a);
+}
+
+// LLVM-LABEL: @test_vcvtd_f64_s64(
+// CIR-LABEL: @vcvtd_f64_s64(
+float64_t test_vcvtd_f64_s64(int64_t a) {
+// CIR: cir.cast int_to_float
+
+// LLVM-SAME: i64 {{.*}} [[A:%.*]])
+// LLVM: [[TMP0:%.*]] = sitofp i64 [[A]] to double
+// LLVM: ret double [[TMP0]]
+ return vcvtd_f64_s64(a);
+}
+
+// LLVM-LABEL: @test_vcvtd_f64_u64(
+// CIR-LABEL: @vcvtd_f64_u64(
+float64_t test_vcvtd_f64_u64(uint64_t a) {
+// CIR: cir.cast int_to_float
+
+// LLVM-SAME: i64 {{.*}} [[A:%.*]]) #[[ATTR0]] {
+// LLVM: [[TMP0:%.*]] = uitofp i64 [[A]] to double
+// LLVM: ret double [[TMP0]]
+ return vcvtd_f64_u64(a);
+}
+
+//===------------------------------------------------------===//
+// 2.1.4.1 Convearions (float width conversion)
+// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#conversions
+//===------------------------------------------------------===//
+// LLVM-LABEL: @test_vcvt_f16_f32(
+// CIR-LABEL: @vcvt_f16_f32(
+float16x4_t test_vcvt_f16_f32(float32x4_t a) {
+// CIR: cir.cast floating
----------------
andykaylor wrote:
I'm seeing a failure on this line.
https://github.com/llvm/llvm-project/pull/217263
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