https://github.com/TelGome created https://github.com/llvm/llvm-project/pull/215779
This pr support RISC-V P extension intrinsics [Packed Narrowing Clip Pair](https://github.com/riscv/riscv-p-spec/blob/master/P-ext-intrinsics.adoc#packed-narrowing-clip-pair) >From 1d8da95be0dafa0a9a7279ce7a587587fb5cfe90 Mon Sep 17 00:00:00 2001 From: Dongyan Chen <[email protected]> Date: Wed, 12 Aug 2026 09:00:24 +0000 Subject: [PATCH] [RISCV][P-ext] Support Packed Narrowing Clip Pair --- clang/include/clang/Basic/BuiltinsRISCV.td | 14 ++ clang/lib/CodeGen/TargetBuiltins/RISCV.cpp | 27 ++- clang/lib/Headers/riscv_packed_simd.h | 14 ++ clang/test/CodeGen/RISCV/rvp-intrinsics.c | 208 ++++++++++++++++++ .../riscv_packed_simd.c | 76 +++++++ llvm/include/llvm/IR/IntrinsicsRISCV.td | 8 + llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 97 ++++++++ llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 28 +++ llvm/test/CodeGen/RISCV/rvp-simd-32.ll | 103 +++++++++ llvm/test/CodeGen/RISCV/rvp-simd-64.ll | 99 +++++++++ 10 files changed, 673 insertions(+), 1 deletion(-) diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td index 1e55ab0bc56d5..82e8a2b62e645 100644 --- a/clang/include/clang/Basic/BuiltinsRISCV.td +++ b/clang/include/clang/Basic/BuiltinsRISCV.td @@ -275,6 +275,20 @@ def pmulqr_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>, _Vector<4, def pmulq_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2, int>)">; def pmulqr_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2, int>)">; +// Packed Narrowing Clip Pair (32-bit) +def pnclipp_i8x4 : RISCVBuiltin<"_Vector<4, signed char>(_Vector<2, short>, _Vector<2, short>)">; +def pnclipup_u8x4 : RISCVBuiltin<"_Vector<4, unsigned char>(_Vector<2, unsigned short>, _Vector<2, unsigned short>)">; +def pnclipp_i16x2 : RISCVBuiltin<"_Vector<2, short>(int, int)">; +def pnclipup_u16x2 : RISCVBuiltin<"_Vector<2, unsigned short>(unsigned int, unsigned int)">; + +// Packed Narrowing Clip Pair (64-bit) +def pnclipp_i8x8 : RISCVBuiltin<"_Vector<8, signed char>(_Vector<4, short>, _Vector<4, short>)">; +def pnclipup_u8x8 : RISCVBuiltin<"_Vector<8, unsigned char>(_Vector<4, unsigned short>, _Vector<4, unsigned short>)">; +def pnclipp_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<2, int>, _Vector<2, int>)">; +def pnclipup_u16x4 : RISCVBuiltin<"_Vector<4, unsigned short>(_Vector<2, unsigned int>, _Vector<2, unsigned int>)">; +def pnclipp_i32x2 : RISCVBuiltin<"_Vector<2, int>(int64_t, int64_t)">; +def pnclipup_u32x2 : RISCVBuiltin<"_Vector<2, unsigned int>(uint64_t, uint64_t)">; + } // Features = "experimental-p" //===----------------------------------------------------------------------===// diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp index 65e43e928e1f0..189352468e1c0 100644 --- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp @@ -1392,7 +1392,18 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, case RISCV::BI__builtin_riscv_predsumu_u16x4_u32: case RISCV::BI__builtin_riscv_predsumu_u8x8_u64: case RISCV::BI__builtin_riscv_predsumu_u16x4_u64: - case RISCV::BI__builtin_riscv_predsumu_u32x2_u64: { + case RISCV::BI__builtin_riscv_predsumu_u32x2_u64: + // Packed Narrowing Clip Pair + case RISCV::BI__builtin_riscv_pnclipp_i8x4: + case RISCV::BI__builtin_riscv_pnclipp_i8x8: + case RISCV::BI__builtin_riscv_pnclipp_i16x2: + case RISCV::BI__builtin_riscv_pnclipp_i16x4: + case RISCV::BI__builtin_riscv_pnclipp_i32x2: + case RISCV::BI__builtin_riscv_pnclipup_u8x4: + case RISCV::BI__builtin_riscv_pnclipup_u8x8: + case RISCV::BI__builtin_riscv_pnclipup_u16x2: + case RISCV::BI__builtin_riscv_pnclipup_u16x4: + case RISCV::BI__builtin_riscv_pnclipup_u32x2: { switch (BuiltinID) { default: llvm_unreachable("unexpected builtin ID"); @@ -1414,6 +1425,20 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID, case RISCV::BI__builtin_riscv_predsumu_u32x2_u64: ID = Intrinsic::riscv_predsumu; break; + case RISCV::BI__builtin_riscv_pnclipp_i8x4: + case RISCV::BI__builtin_riscv_pnclipp_i8x8: + case RISCV::BI__builtin_riscv_pnclipp_i16x2: + case RISCV::BI__builtin_riscv_pnclipp_i16x4: + case RISCV::BI__builtin_riscv_pnclipp_i32x2: + ID = Intrinsic::riscv_pnclipp; + break; + case RISCV::BI__builtin_riscv_pnclipup_u8x4: + case RISCV::BI__builtin_riscv_pnclipup_u8x8: + case RISCV::BI__builtin_riscv_pnclipup_u16x2: + case RISCV::BI__builtin_riscv_pnclipup_u16x4: + case RISCV::BI__builtin_riscv_pnclipup_u32x2: + ID = Intrinsic::riscv_pnclipup; + break; } IntrinsicTypes = {ResultType, Ops[0]->getType()}; diff --git a/clang/lib/Headers/riscv_packed_simd.h b/clang/lib/Headers/riscv_packed_simd.h index ded18175b7453..bcaa3e0f29c0e 100644 --- a/clang/lib/Headers/riscv_packed_simd.h +++ b/clang/lib/Headers/riscv_packed_simd.h @@ -742,6 +742,20 @@ __packed_binary_builtin(pmulqr_i16x4, int16x4_t, __builtin_riscv_pmulqr_i16x4) __packed_binary_builtin(pmulq_i32x2, int32x2_t, __builtin_riscv_pmulq_i32x2) __packed_binary_builtin(pmulqr_i32x2, int32x2_t, __builtin_riscv_pmulqr_i32x2) +/* Packed Narrowing Clip Pair (32-bit) */ +__packed_binary_builtin_cast(pnclipp_i8x4, int16x2_t, int8x4_t, __builtin_riscv_pnclipp_i8x4) +__packed_binary_builtin_cast(pnclipup_u8x4, uint16x2_t, uint8x4_t, __builtin_riscv_pnclipup_u8x4) +__packed_binary_builtin_cast(pnclipp_i16x2, int, int16x2_t, __builtin_riscv_pnclipp_i16x2) +__packed_binary_builtin_cast(pnclipup_u16x2, unsigned int, uint16x2_t, __builtin_riscv_pnclipup_u16x2) + +/* Packed Narrowing Clip Pair (64-bit) */ +__packed_binary_builtin_cast(pnclipp_i8x8, int16x4_t, int8x8_t, __builtin_riscv_pnclipp_i8x8) +__packed_binary_builtin_cast(pnclipup_u8x8, uint16x4_t, uint8x8_t, __builtin_riscv_pnclipup_u8x8) +__packed_binary_builtin_cast(pnclipp_i16x4, int32x2_t, int16x4_t, __builtin_riscv_pnclipp_i16x4) +__packed_binary_builtin_cast(pnclipup_u16x4, uint32x2_t, uint16x4_t, __builtin_riscv_pnclipup_u16x4) +__packed_binary_builtin_cast(pnclipp_i32x2, int64_t, int32x2_t, __builtin_riscv_pnclipp_i32x2) +__packed_binary_builtin_cast(pnclipup_u32x2, uint64_t, uint32x2_t, __builtin_riscv_pnclipup_u32x2) + /* Reinterpret Casts, Packed <-> Scalar (32-bit) */ __packed_reinterpret(u8x4_u32, uint32_t, uint8x4_t) __packed_reinterpret(u16x2_u32, uint32_t, uint16x2_t) diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c b/clang/test/CodeGen/RISCV/rvp-intrinsics.c index 9ba0428e192f0..4fd28e5919ff6 100644 --- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c +++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c @@ -9353,3 +9353,211 @@ int16x4_t test_pnziph_i16x4(int32x2_t rs1, int32x2_t rs2) { uint16x4_t test_pnziph_u16x4(uint32x2_t rs1, uint32x2_t rs2) { return __riscv_pnziph_u16x4(rs1, rs2); } + +/* Packed Narrowing Clip Pair (32-bit) */ + +// RV32-LABEL: define dso_local i32 @test_pnclipp_i8x4( +// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pnclipp.v4i8.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32 +// RV32-NEXT: ret i32 [[TMP3]] +// +// RV64-LABEL: define dso_local i32 @test_pnclipp_i8x4( +// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pnclipp.v4i8.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32 +// RV64-NEXT: ret i32 [[TMP3]] +// +int8x4_t test_pnclipp_i8x4(int16x2_t rs1, int16x2_t rs2) { + return __riscv_pnclipp_i8x4(rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pnclipup_u8x4( +// RV32-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV32-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pnclipup.v4i8.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32 +// RV32-NEXT: ret i32 [[TMP3]] +// +// RV64-LABEL: define dso_local i32 @test_pnclipup_u8x4( +// RV64-SAME: i32 noundef [[RS1_COERCE:%.*]], i32 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[RS1_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[RS2_COERCE]] to <2 x i16> +// RV64-NEXT: [[TMP2:%.*]] = call <4 x i8> @llvm.riscv.pnclipup.v4i8.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]]) +// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i8> [[TMP2]] to i32 +// RV64-NEXT: ret i32 [[TMP3]] +// +uint8x4_t test_pnclipup_u8x4(uint16x2_t rs1, uint16x2_t rs2) { + return __riscv_pnclipup_u8x4(rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pnclipp_i16x2( +// RV32-SAME: i32 noundef [[RS1:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.riscv.pnclipp.v2i16.i32(i32 [[RS1]], i32 [[RS2]]) +// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[TMP0]] to i32 +// RV32-NEXT: ret i32 [[TMP1]] +// +// RV64-LABEL: define dso_local i32 @test_pnclipp_i16x2( +// RV64-SAME: i32 noundef signext [[RS1:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.riscv.pnclipp.v2i16.i32(i32 [[RS1]], i32 [[RS2]]) +// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[TMP0]] to i32 +// RV64-NEXT: ret i32 [[TMP1]] +// +int16x2_t test_pnclipp_i16x2(int32_t rs1, int32_t rs2) { + return __riscv_pnclipp_i16x2(rs1, rs2); +} + +// RV32-LABEL: define dso_local i32 @test_pnclipup_u16x2( +// RV32-SAME: i32 noundef [[RS1:%.*]], i32 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.riscv.pnclipup.v2i16.i32(i32 [[RS1]], i32 [[RS2]]) +// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[TMP0]] to i32 +// RV32-NEXT: ret i32 [[TMP1]] +// +// RV64-LABEL: define dso_local i32 @test_pnclipup_u16x2( +// RV64-SAME: i32 noundef signext [[RS1:%.*]], i32 noundef signext [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.riscv.pnclipup.v2i16.i32(i32 [[RS1]], i32 [[RS2]]) +// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i16> [[TMP0]] to i32 +// RV64-NEXT: ret i32 [[TMP1]] +// +uint16x2_t test_pnclipup_u16x2(uint32_t rs1, uint32_t rs2) { + return __riscv_pnclipup_u16x2(rs1, rs2); +} + +/* Packed Narrowing Clip Pair (64-bit) */ + +// RV32-LABEL: define dso_local i64 @test_pnclipp_i8x8( +// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16> +// RV32-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pnclipp.v8i8.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) +// RV32-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64 +// RV32-NEXT: ret i64 [[TMP3]] +// +// RV64-LABEL: define dso_local i64 @test_pnclipp_i8x8( +// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16> +// RV64-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pnclipp.v8i8.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) +// RV64-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64 +// RV64-NEXT: ret i64 [[TMP3]] +// +int8x8_t test_pnclipp_i8x8(int16x4_t rs1, int16x4_t rs2) { + return __riscv_pnclipp_i8x8(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pnclipup_u8x8( +// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16> +// RV32-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pnclipup.v8i8.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) +// RV32-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64 +// RV32-NEXT: ret i64 [[TMP3]] +// +// RV64-LABEL: define dso_local i64 @test_pnclipup_u8x8( +// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <4 x i16> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <4 x i16> +// RV64-NEXT: [[TMP2:%.*]] = call <8 x i8> @llvm.riscv.pnclipup.v8i8.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]]) +// RV64-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to i64 +// RV64-NEXT: ret i64 [[TMP3]] +// +uint8x8_t test_pnclipup_u8x8(uint16x4_t rs1, uint16x4_t rs2) { + return __riscv_pnclipup_u8x8(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pnclipp_i16x4( +// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32> +// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pnclipp.v4i16.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) +// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64 +// RV32-NEXT: ret i64 [[TMP3]] +// +// RV64-LABEL: define dso_local i64 @test_pnclipp_i16x4( +// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32> +// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pnclipp.v4i16.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) +// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64 +// RV64-NEXT: ret i64 [[TMP3]] +// +int16x4_t test_pnclipp_i16x4(int32x2_t rs1, int32x2_t rs2) { + return __riscv_pnclipp_i16x4(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pnclipup_u16x4( +// RV32-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> +// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32> +// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pnclipup.v4i16.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) +// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64 +// RV32-NEXT: ret i64 [[TMP3]] +// +// RV64-LABEL: define dso_local i64 @test_pnclipup_u16x4( +// RV64-SAME: i64 noundef [[RS1_COERCE:%.*]], i64 noundef [[RS2_COERCE:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[RS1_COERCE]] to <2 x i32> +// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[RS2_COERCE]] to <2 x i32> +// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pnclipup.v4i16.v2i32(<2 x i32> [[TMP0]], <2 x i32> [[TMP1]]) +// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64 +// RV64-NEXT: ret i64 [[TMP3]] +// +uint16x4_t test_pnclipup_u16x4(uint32x2_t rs1, uint32x2_t rs2) { + return __riscv_pnclipup_u16x4(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pnclipp_i32x2( +// RV32-SAME: i64 noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.riscv.pnclipp.v2i32.i64(i64 [[RS1]], i64 [[RS2]]) +// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to i64 +// RV32-NEXT: ret i64 [[TMP1]] +// +// RV64-LABEL: define dso_local i64 @test_pnclipp_i32x2( +// RV64-SAME: i64 noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.riscv.pnclipp.v2i32.i64(i64 [[RS1]], i64 [[RS2]]) +// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to i64 +// RV64-NEXT: ret i64 [[TMP1]] +// +int32x2_t test_pnclipp_i32x2(int64_t rs1, int64_t rs2) { + return __riscv_pnclipp_i32x2(rs1, rs2); +} + +// RV32-LABEL: define dso_local i64 @test_pnclipup_u32x2( +// RV32-SAME: i64 noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV32-NEXT: [[ENTRY:.*:]] +// RV32-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.riscv.pnclipup.v2i32.i64(i64 [[RS1]], i64 [[RS2]]) +// RV32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to i64 +// RV32-NEXT: ret i64 [[TMP1]] +// +// RV64-LABEL: define dso_local i64 @test_pnclipup_u32x2( +// RV64-SAME: i64 noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]]) #[[ATTR0]] { +// RV64-NEXT: [[ENTRY:.*:]] +// RV64-NEXT: [[TMP0:%.*]] = call <2 x i32> @llvm.riscv.pnclipup.v2i32.i64(i64 [[RS1]], i64 [[RS2]]) +// RV64-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to i64 +// RV64-NEXT: ret i64 [[TMP1]] +// +uint32x2_t test_pnclipup_u32x2(uint64_t rs1, uint64_t rs2) { + return __riscv_pnclipup_u32x2(rs1, rs2); +} diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c index 874ae879ae488..6c225288756af 100644 --- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c +++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c @@ -2847,3 +2847,79 @@ uint16x2_t test_punzipe_u16x2(uint16x4_t a) { return __riscv_punzipe_u16x2(a); } // RV32: pncvth.h // RV64: pncvth.wh uint16x2_t test_punzipo_u16x2(uint16x4_t a) { return __riscv_punzipo_u16x2(a); } + +// CHECK-LABEL: test_pnclipp_i8x4: +// RV32: pnclipi.b +// RV64: pnclipp.b +int8x4_t test_pnclipp_i8x4(int16x2_t a, int16x2_t b) { + return __riscv_pnclipp_i8x4(a, b); +} + +// CHECK-LABEL: test_pnclipup_u8x4: +// RV32: pnclipiu.b +// RV64: pnclipup.b +uint8x4_t test_pnclipup_u8x4(uint16x2_t a, uint16x2_t b) { + return __riscv_pnclipup_u8x4(a, b); +} + +// CHECK-LABEL: test_pnclipp_i16x2: +// RV32: pnclipi.h +// RV64: pnclipp.h +int16x2_t test_pnclipp_i16x2(int32_t a, int32_t b) { + return __riscv_pnclipp_i16x2(a, b); +} + +// CHECK-LABEL: test_pnclipup_u16x2: +// RV32: pnclipiu.h +// RV64: pnclipup.h +uint16x2_t test_pnclipup_u16x2(uint32_t a, uint32_t b) { + return __riscv_pnclipup_u16x2(a, b); +} + +// CHECK-LABEL: test_pnclipp_i8x8: +// RV32: pnclipi.b +// RV32: pnclipi.b +// RV64: pnclipp.b +int8x8_t test_pnclipp_i8x8(int16x4_t a, int16x4_t b) { + return __riscv_pnclipp_i8x8(a, b); +} + +// CHECK-LABEL: test_pnclipup_u8x8: +// RV32: pnclipiu.b +// RV32: pnclipiu.b +// RV64: pnclipup.b +uint8x8_t test_pnclipup_u8x8(uint16x4_t a, uint16x4_t b) { + return __riscv_pnclipup_u8x8(a, b); +} + +// CHECK-LABEL: test_pnclipp_i16x4: +// RV32: pnclipi.h +// RV32: pnclipi.h +// RV64: pnclipp.h +int16x4_t test_pnclipp_i16x4(int32x2_t a, int32x2_t b) { + return __riscv_pnclipp_i16x4(a, b); +} + +// CHECK-LABEL: test_pnclipup_u16x4: +// RV32: pnclipiu.h +// RV32: pnclipiu.h +// RV64: pnclipup.h +uint16x4_t test_pnclipup_u16x4(uint32x2_t a, uint32x2_t b) { + return __riscv_pnclipup_u16x4(a, b); +} + +// CHECK-LABEL: test_pnclipp_i32x2: +// RV32: nclipi +// RV32: nclipi +// RV64: pnclipp.w +int32x2_t test_pnclipp_i32x2(int64_t a, int64_t b) { + return __riscv_pnclipp_i32x2(a, b); +} + +// CHECK-LABEL: test_pnclipup_u32x2: +// RV32: nclipiu +// RV32: nclipiu +// RV64: pnclipup.w +uint32x2_t test_pnclipup_u32x2(uint64_t a, uint64_t b) { + return __riscv_pnclipup_u32x2(a, b); +} diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td index 6e3de3bfbc309..81fa98bf5bda5 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -2126,6 +2126,14 @@ class RVPBinaryIntrinsic [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]>; def int_riscv_psabs : RVPUnaryIntrinsic; + + // Packed Narrowing Clip Pair + class RVPNarrowingClipIntrinsic + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], + [llvm_any_ty, LLVMMatchType<1>], + [IntrNoMem, IntrSpeculatable]>; + def int_riscv_pnclipp : RVPNarrowingClipIntrinsic; + def int_riscv_pnclipup : RVPNarrowingClipIntrinsic; } // TargetPrefix = "riscv" //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index ea4803e59ebc1..ef7b4ce4b786e 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -12283,6 +12283,77 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, return DAG.getNode(Opc, DL, Op.getValueType(), Op.getOperand(1), Op.getOperand(2)); } + case Intrinsic::riscv_pnclipp: + case Intrinsic::riscv_pnclipup: { + EVT VT = Op.getValueType(); + SDValue Rs1 = Op.getOperand(1); + SDValue Rs2 = Op.getOperand(2); + unsigned Opc = IntNo == Intrinsic::riscv_pnclipp ? RISCVISD::PNCLIPP + : RISCVISD::PNCLIPUP; + + if (Subtarget.is64Bit()) { + if (VT == MVT::v2i32 && !Rs1.getValueType().isVector()) { + unsigned WOpc = IntNo == Intrinsic::riscv_pnclipp + ? RISCVISD::PNCLIPP_W + : RISCVISD::PNCLIPUP_W; + return DAG.getNode(WOpc, DL, VT, Rs1, Rs2); + } + return DAG.getNode(Opc, DL, VT, Rs1, Rs2); + } + + auto BuildPair = [&](SDValue Lo, SDValue Hi, MVT PairVT) { + return DAG.getNode(RISCVISD::BuildPairGPRVec, DL, PairVT, Lo, Hi); + }; + + MVT XLenVT = Subtarget.getXLenVT(); + if (VT == MVT::v4i8) { + SDValue Pair = BuildPair(Rs1, Rs2, MVT::v4i16); + SDVTList VTs = DAG.getVTList(MVT::v4i8); + unsigned ClipOpc = IntNo == Intrinsic::riscv_pnclipp ? RISCV::PNCLIPI_B + : RISCV::PNCLIPIU_B; + SDValue Ops[] = {Pair, DAG.getTargetConstant(0, DL, MVT::i32)}; + return SDValue(DAG.getMachineNode(ClipOpc, DL, VTs, Ops), 0); + } + if (VT == MVT::v2i16) { + unsigned HOpc = IntNo == Intrinsic::riscv_pnclipp ? RISCV::PNCLIPI_H + : RISCV::PNCLIPIU_H; + SDVTList VTs = DAG.getVTList(MVT::v2i16); + SDValue Pair = BuildPair(Rs1, Rs2, MVT::v2i32); + SDValue Ops[] = {Pair, DAG.getTargetConstant(0, DL, MVT::i32)}; + return SDValue(DAG.getMachineNode(HOpc, DL, VTs, Ops), 0); + } + if (VT == MVT::v2i32) { + unsigned NOpc = + IntNo == Intrinsic::riscv_pnclipp ? RISCV::NCLIPI : RISCV::NCLIPIU; + SDVTList VTs = DAG.getVTList(XLenVT); + SDValue Zero = DAG.getTargetConstant(0, DL, MVT::i32); + auto BuildPairFromI64 = [&](SDValue I64) { + SDValue Vec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, I64); + SDValue Lo = DAG.getExtractVectorElt(DL, XLenVT, Vec, 0); + SDValue Hi = DAG.getExtractVectorElt(DL, XLenVT, Vec, 1); + return DAG.getNode(RISCVISD::BuildGPRPair, DL, MVT::Untyped, Lo, Hi); + }; + SDValue Pair1 = BuildPairFromI64(Rs1); + SDValue Pair2 = BuildPairFromI64(Rs2); + SDValue Lo = SDValue(DAG.getMachineNode(NOpc, DL, VTs, {Pair1, Zero}), 0); + SDValue Hi = SDValue(DAG.getMachineNode(NOpc, DL, VTs, {Pair2, Zero}), 0); + return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Lo, Hi); + } + if (VT == MVT::v8i8 || VT == MVT::v4i16) { + unsigned HOpc = + IntNo == Intrinsic::riscv_pnclipp + ? (VT == MVT::v8i8 ? RISCV::PNCLIPI_B : RISCV::PNCLIPI_H) + : (VT == MVT::v8i8 ? RISCV::PNCLIPIU_B : RISCV::PNCLIPIU_H); + MVT HalfVT = VT == MVT::v8i8 ? MVT::v4i8 : MVT::v2i16; + SDVTList VTs = DAG.getVTList(HalfVT); + SDValue Zero = DAG.getTargetConstant(0, DL, MVT::i32); + SDValue Lo = SDValue(DAG.getMachineNode(HOpc, DL, VTs, {Rs1, Zero}), 0); + SDValue Hi = SDValue(DAG.getMachineNode(HOpc, DL, VTs, {Rs2, Zero}), 0); + return DAG.getNode(RISCVISD::BuildPairGPRVec, DL, VT, Lo, Hi); + } + + return DAG.getNode(Opc, DL, VT, Rs1, Rs2); + } case Intrinsic::riscv_pmulq: case Intrinsic::riscv_pmulqr: { unsigned Opc; @@ -16527,6 +16598,32 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N, DAG.getVectorIdxConstant(0, DL))); return; } + case Intrinsic::riscv_pnclipp: + case Intrinsic::riscv_pnclipup: { + EVT VT = N->getValueType(0); + if (!Subtarget.is64Bit() || (VT != MVT::v4i8 && VT != MVT::v2i16)) + return; + unsigned Opc = IntNo == Intrinsic::riscv_pnclipp ? RISCVISD::PNCLIPP + : RISCVISD::PNCLIPUP; + SDValue Src1 = N->getOperand(1); + SDValue Src2 = N->getOperand(2); + if (VT == MVT::v4i8) { + MVT WideSrcVT = MVT::v4i16; + SDValue Packed = + DAG.getNode(ISD::CONCAT_VECTORS, DL, WideSrcVT, {Src1, Src2}); + SDValue Res = DAG.getNode(Opc, DL, MVT::v8i8, {Packed, Packed}); + Results.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Res, + DAG.getVectorIdxConstant(0, DL))); + } else { + MVT WideSrcVT = MVT::v2i32; + SDValue Packed = + DAG.getNode(ISD::BUILD_VECTOR, DL, WideSrcVT, {Src1, Src2}); + SDValue Res = DAG.getNode(Opc, DL, MVT::v4i16, {Packed, Packed}); + Results.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Res, + DAG.getVectorIdxConstant(0, DL))); + } + return; + } case Intrinsic::riscv_pssha: case Intrinsic::riscv_psshar: case Intrinsic::riscv_psshl: diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td index b5cd4c1aad196..70686f51f4156 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td @@ -1908,6 +1908,20 @@ def SDT_RISCVPackedNarrowingShift SDTCisVT<2, XLenVT>]>; def riscv_pnsrl : RVSDNode<"PNSRL", SDT_RISCVPackedNarrowingShift>; +// Packed narrowing clip pair. +def SDT_RISCVPackedNarrowingClip + : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, + SDTCisSameAs<1, 2>]>; +def riscv_pnclipp : RVSDNode<"PNCLIPP", SDT_RISCVPackedNarrowingClip>; +def riscv_pnclipup : RVSDNode<"PNCLIPUP", SDT_RISCVPackedNarrowingClip>; + +def SDT_RISCVPackedNarrowingClipW + : SDTypeProfile<1, 2, [SDTCisVT<0, v2i32>, + SDTCisVT<1, XLenVT>, + SDTCisSameAs<1, 2>]>; +def riscv_pnclipp_w : RVSDNode<"PNCLIPP_W", SDT_RISCVPackedNarrowingClipW>; +def riscv_pnclipup_w : RVSDNode<"PNCLIPUP_W", SDT_RISCVPackedNarrowingClipW>; + // The immediate for these is the number of trailing ones in the max value. def riscv_sati : RVSDNode<"SATI", SDTIntBinOp>; def riscv_usati : RVSDNode<"USATI", SDTIntBinOp>; @@ -2639,6 +2653,20 @@ let append Predicates = [IsRV64] in { def : PatGpr<bitreverse, REV_RV64>; + // Packed narrowing clip pair. + def : Pat<(v8i8 (riscv_pnclipp (v4i16 GPR:$rs1), (v4i16 GPR:$rs2))), + (PNCLIPP_B GPR:$rs1, GPR:$rs2)>; + def : Pat<(v4i16 (riscv_pnclipp (v2i32 GPR:$rs1), (v2i32 GPR:$rs2))), + (PNCLIPP_H GPR:$rs1, GPR:$rs2)>; + def : Pat<(v8i8 (riscv_pnclipup (v4i16 GPR:$rs1), (v4i16 GPR:$rs2))), + (PNCLIPUP_B GPR:$rs1, GPR:$rs2)>; + def : Pat<(v4i16 (riscv_pnclipup (v2i32 GPR:$rs1), (v2i32 GPR:$rs2))), + (PNCLIPUP_H GPR:$rs1, GPR:$rs2)>; + def : Pat<(v2i32 (riscv_pnclipp_w GPR:$rs1, GPR:$rs2)), + (PNCLIPP_W GPR:$rs1, GPR:$rs2)>; + def : Pat<(v2i32 (riscv_pnclipup_w GPR:$rs1, GPR:$rs2)), + (PNCLIPUP_W GPR:$rs1, GPR:$rs2)>; + def : Pat<(XLenVT (riscv_sati GPR:$rs1, timm:$imm)), (SATI_RV64 GPR:$rs1, (IncImm timm:$imm))>; def : Pat<(XLenVT (riscv_usati GPR:$rs1, timm:$imm)), diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll index c85b0091de487..ff1591f4b8f95 100644 --- a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll +++ b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll @@ -2828,3 +2828,106 @@ define <2 x i16> @test_pmulqr_v2i16(<2 x i16> %a, <2 x i16> %b) { %res = call <2 x i16> @llvm.riscv.pmulqr.v2i16(<2 x i16> %a, <2 x i16> %b) ret <2 x i16> %res } + +define <4 x i8> @test_pnclipp_v4i8(<2 x i16> %a, <2 x i16> %b) { +; RV32-LABEL: test_pnclipp_v4i8: +; RV32: # %bb.0: +; RV32-NEXT: pnclipi.b a0, a0, 0 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipp_v4i8: +; RV64: # %bb.0: +; RV64-NEXT: srli a2, a1, 16 +; RV64-NEXT: srli a3, a0, 16 +; RV64-NEXT: ppaire.h a1, a1, a2 +; RV64-NEXT: ppaire.h a0, a0, a3 +; RV64-NEXT: pack a0, a0, a1 +; RV64-NEXT: pnclipp.b a0, a0, a0 +; RV64-NEXT: ret + %r = call <4 x i8> @llvm.riscv.pnclipp.v4i8.v2i16(<2 x i16> %a, <2 x i16> %b) + ret <4 x i8> %r +} + +define <4 x i8> @test_pnclipup_v4i8(<2 x i16> %a, <2 x i16> %b) { +; RV32-LABEL: test_pnclipup_v4i8: +; RV32: # %bb.0: +; RV32-NEXT: pnclipiu.b a0, a0, 0 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipup_v4i8: +; RV64: # %bb.0: +; RV64-NEXT: srli a2, a1, 16 +; RV64-NEXT: srli a3, a0, 16 +; RV64-NEXT: ppaire.h a1, a1, a2 +; RV64-NEXT: ppaire.h a0, a0, a3 +; RV64-NEXT: pack a0, a0, a1 +; RV64-NEXT: pnclipup.b a0, a0, a0 +; RV64-NEXT: ret + %r = call <4 x i8> @llvm.riscv.pnclipup.v4i8.v2i16(<2 x i16> %a, <2 x i16> %b) + ret <4 x i8> %r +} + +define <2 x i16> @test_pnclipp_v2i16(i32 %a, i32 %b) { +; RV32-LABEL: test_pnclipp_v2i16: +; RV32: # %bb.0: +; RV32-NEXT: pnclipi.h a0, a0, 0 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipp_v2i16: +; RV64: # %bb.0: +; RV64-NEXT: pack a0, a0, a1 +; RV64-NEXT: pnclipp.h a0, a0, a0 +; RV64-NEXT: ret + %r = call <2 x i16> @llvm.riscv.pnclipp.v2i16.i32(i32 %a, i32 %b) + ret <2 x i16> %r +} + +define <2 x i16> @test_pnclipup_v2i16(i32 %a, i32 %b) { +; RV32-LABEL: test_pnclipup_v2i16: +; RV32: # %bb.0: +; RV32-NEXT: pnclipiu.h a0, a0, 0 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipup_v2i16: +; RV64: # %bb.0: +; RV64-NEXT: pack a0, a0, a1 +; RV64-NEXT: pnclipup.h a0, a0, a0 +; RV64-NEXT: ret + %r = call <2 x i16> @llvm.riscv.pnclipup.v2i16.i32(i32 %a, i32 %b) + ret <2 x i16> %r +} + +declare <2 x i32> @llvm.riscv.pnclipp.v2i32.i64(i64, i64) +declare <2 x i32> @llvm.riscv.pnclipup.v2i32.i64(i64, i64) + +define i64 @test_pnclipp_v2i32_i64(i64 %a, i64 %b) { +; RV32-LABEL: test_pnclipp_v2i32_i64: +; RV32: # %bb.0: +; RV32-NEXT: nclipi a0, a0, 0 +; RV32-NEXT: nclipi a1, a2, 0 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipp_v2i32_i64: +; RV64: # %bb.0: +; RV64-NEXT: pnclipp.w a0, a0, a1 +; RV64-NEXT: ret + %r = call <2 x i32> @llvm.riscv.pnclipp.v2i32.i64(i64 %a, i64 %b) + %s = bitcast <2 x i32> %r to i64 + ret i64 %s +} + +define i64 @test_pnclipup_v2i32_i64(i64 %a, i64 %b) { +; RV32-LABEL: test_pnclipup_v2i32_i64: +; RV32: # %bb.0: +; RV32-NEXT: nclipiu a0, a0, 0 +; RV32-NEXT: nclipiu a1, a2, 0 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipup_v2i32_i64: +; RV64: # %bb.0: +; RV64-NEXT: pnclipup.w a0, a0, a1 +; RV64-NEXT: ret + %r = call <2 x i32> @llvm.riscv.pnclipup.v2i32.i64(i64 %a, i64 %b) + %s = bitcast <2 x i32> %r to i64 + ret i64 %s +} diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll index d31942feb113b..13f66716ced14 100644 --- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll +++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll @@ -6371,3 +6371,102 @@ define <8 x i8> @test_ppair_v2_used_twice_v8i8(<8 x i8> %a, <8 x i8> %b) { %res = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14> ret <8 x i8> %res } + +define <8 x i8> @test_pnclipp_v8i8(<4 x i16> %a, <4 x i16> %b) { +; RV32-LABEL: test_pnclipp_v8i8: +; RV32: # %bb.0: +; RV32-NEXT: pnclipi.b a2, a2, 0 +; RV32-NEXT: pnclipi.b a0, a0, 0 +; RV32-NEXT: mv a1, a2 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipp_v8i8: +; RV64: # %bb.0: +; RV64-NEXT: pnclipp.b a0, a0, a1 +; RV64-NEXT: ret + %r = call <8 x i8> @llvm.riscv.pnclipp.v8i8.v4i16(<4 x i16> %a, <4 x i16> %b) + ret <8 x i8> %r +} + +define <8 x i8> @test_pnclipup_v8i8(<4 x i16> %a, <4 x i16> %b) { +; RV32-LABEL: test_pnclipup_v8i8: +; RV32: # %bb.0: +; RV32-NEXT: pnclipiu.b a2, a2, 0 +; RV32-NEXT: pnclipiu.b a0, a0, 0 +; RV32-NEXT: mv a1, a2 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipup_v8i8: +; RV64: # %bb.0: +; RV64-NEXT: pnclipup.b a0, a0, a1 +; RV64-NEXT: ret + %r = call <8 x i8> @llvm.riscv.pnclipup.v8i8.v4i16(<4 x i16> %a, <4 x i16> %b) + ret <8 x i8> %r +} + +define <4 x i16> @test_pnclipp_v4i16(<2 x i32> %a, <2 x i32> %b) { +; RV32-LABEL: test_pnclipp_v4i16: +; RV32: # %bb.0: +; RV32-NEXT: pnclipi.h a2, a2, 0 +; RV32-NEXT: pnclipi.h a0, a0, 0 +; RV32-NEXT: mv a1, a2 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipp_v4i16: +; RV64: # %bb.0: +; RV64-NEXT: pnclipp.h a0, a0, a1 +; RV64-NEXT: ret + %r = call <4 x i16> @llvm.riscv.pnclipp.v4i16.v2i32(<2 x i32> %a, <2 x i32> %b) + ret <4 x i16> %r +} + +define <4 x i16> @test_pnclipup_v4i16(<2 x i32> %a, <2 x i32> %b) { +; RV32-LABEL: test_pnclipup_v4i16: +; RV32: # %bb.0: +; RV32-NEXT: pnclipiu.h a2, a2, 0 +; RV32-NEXT: pnclipiu.h a0, a0, 0 +; RV32-NEXT: mv a1, a2 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipup_v4i16: +; RV64: # %bb.0: +; RV64-NEXT: pnclipup.h a0, a0, a1 +; RV64-NEXT: ret + %r = call <4 x i16> @llvm.riscv.pnclipup.v4i16.v2i32(<2 x i32> %a, <2 x i32> %b) + ret <4 x i16> %r +} + +declare <2 x i32> @llvm.riscv.pnclipp.v2i32.i64(i64, i64) +declare <2 x i32> @llvm.riscv.pnclipup.v2i32.i64(i64, i64) + +define i64 @test_pnclipp_v2i32(i64 %a, i64 %b) { +; RV32-LABEL: test_pnclipp_v2i32: +; RV32: # %bb.0: +; RV32-NEXT: nclipi a0, a0, 0 +; RV32-NEXT: nclipi a1, a2, 0 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipp_v2i32: +; RV64: # %bb.0: +; RV64-NEXT: pnclipp.w a0, a0, a1 +; RV64-NEXT: ret + %r = call <2 x i32> @llvm.riscv.pnclipp.v2i32.i64(i64 %a, i64 %b) + %s = bitcast <2 x i32> %r to i64 + ret i64 %s +} + +define i64 @test_pnclipup_v2i32(i64 %a, i64 %b) { +; RV32-LABEL: test_pnclipup_v2i32: +; RV32: # %bb.0: +; RV32-NEXT: nclipiu a0, a0, 0 +; RV32-NEXT: nclipiu a1, a2, 0 +; RV32-NEXT: ret +; +; RV64-LABEL: test_pnclipup_v2i32: +; RV64: # %bb.0: +; RV64-NEXT: pnclipup.w a0, a0, a1 +; RV64-NEXT: ret + %r = call <2 x i32> @llvm.riscv.pnclipup.v2i32.i64(i64 %a, i64 %b) + %s = bitcast <2 x i32> %r to i64 + ret i64 %s +} _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
