Author: Brandon Wu Date: 2026-08-03T03:26:52Z New Revision: 59f3a48ff016773a6093a27d77f27d71e8b4bff7
URL: https://github.com/llvm/llvm-project/commit/59f3a48ff016773a6093a27d77f27d71e8b4bff7 DIFF: https://github.com/llvm/llvm-project/commit/59f3a48ff016773a6093a27d77f27d71e8b4bff7.diff LOG: [llvm][RISCV] Bump svukte to 1.0 (#211199) The PR updated: https://github.com/riscv/riscv-isa-manual/pull/1564 --------- Co-authored-by: Craig Topper <[email protected]> Added: Modified: clang/test/Driver/print-supported-extensions-riscv.c clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/docs/ReleaseNotes.md llvm/lib/Target/RISCV/RISCVFeatures.td llvm/test/CodeGen/RISCV/attributes.ll llvm/test/MC/RISCV/attribute-arch.s llvm/unittests/TargetParser/RISCVISAInfoTest.cpp Removed: ################################################################################ diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index c1abb1876d64a..01ba220491315 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -273,7 +273,7 @@ // CHECK-NEXT: smcsps 0.19 'Smcsps' (Conditional Stack Pointer Swap at Machine Level) // CHECK-NEXT: smpmpmt 0.6 'Smpmpmt' (PMP-based Memory Types Extension) // CHECK-NEXT: sscsps 0.19 'Sscsps' (Conditional Stack Pointer Swap at Supervisor Level) -// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses) +// CHECK-NEXT: svukte 1.0 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses) // CHECK-NEXT: xqccmt 0.1 'Xqccmt' (Qualcomm 16-bit Table Jump) // CHECK-NEXT: xsfmclic 0.1 'XSfmclic' (SiFive CLIC Machine-mode CSRs) // CHECK-NEXT: xsfsclic 0.1 'XSfsclic' (SiFive CLIC Supervisor-mode CSRs) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index d9423ce4baf17..ae809a6709b98 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -1841,12 +1841,12 @@ // CHECK-SSCTR-EXT: __riscv_ssctr 1000000{{$}} // RUN: %clang --target=riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32i_svukte0p3 -E -dM %s \ +// RUN: -march=rv32i_svukte1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SVUKTE-EXT %s // RUN: %clang --target=riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64i_svukte0p3 -E -dM %s \ +// RUN: -march=rv64i_svukte1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SVUKTE-EXT %s -// CHECK-SVUKTE-EXT: __riscv_svukte 3000{{$}} +// CHECK-SVUKTE-EXT: __riscv_svukte 1000000{{$}} // Misaligned diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index ab9c007505e9b..a76817b87f3c9 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -354,7 +354,7 @@ The primary goal of experimental support is to assist in the process of ratifica LLVM implements the `0.7 release specification <https://github.com/user-attachments/files/16450464/riscv-crypto-spec-vector-extra_v0.0.7.pdf>`__. ``experimental-svukte`` - LLVM implements the `0.3 draft specification <https://github.com/riscv/riscv-isa-manual/pull/1564>`__. + LLVM implements the `1.0 draft specification <https://github.com/riscv/riscv-isa-manual/pull/1564>`__. ``experimental-zvdot4a8i`` LLVM implements the `0.1 draft specification <https://github.com/riscv/riscv-isa-manual/pull/2576>`__. diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 10b8ede9dbdf7..34e5c98ad8272 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -98,6 +98,8 @@ Makes programs 10x faster by doing Special New Thing. * Adds experimental assembler/CodeGen support for the `Zilx` (Indexed Integer Load) extension. +* Bump Svukte extension to 1.0. + ### Changes to the WebAssembly Backend ### Changes to the Windows Target diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 3f48aeb01c641..87eaca609b426 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1197,7 +1197,7 @@ def FeatureStdExtSha FeatureStdExtShvsatpa, FeatureStdExtShgatpa]>; def FeatureStdExtSvukte - : RISCVExperimentalExtension<0, 3, + : RISCVExperimentalExtension<1, 0, "Address-Independent Latency of User-Mode Faults to Supervisor Addresses">; // Pointer Masking extensions diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index e5f1aa0292dd9..c83c52c96eb87 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -414,7 +414,7 @@ ; RV32SVBARE: .attribute 5, "rv32i2p1_svbare1p0" ; RV32SVNAPOT: .attribute 5, "rv32i2p1_svnapot1p0" ; RV32SVPBMT: .attribute 5, "rv32i2p1_svpbmt1p0" -; RV32SVUKTE: .attribute 5, "rv32i2p1_svukte0p3" +; RV32SVUKTE: .attribute 5, "rv32i2p1_svukte1p0" ; RV32SVVPTC: .attribute 5, "rv32i2p1_svvptc1p0" ; RV32SVRSW60T59B: .attribute 5, "rv32i2p1_svrsw60t59b1p0" ; RV32SVINVAL: .attribute 5, "rv32i2p1_svinval1p0" @@ -579,7 +579,7 @@ ; RV64SVBARE: .attribute 5, "rv64i2p1_svbare1p0" ; RV64SVNAPOT: .attribute 5, "rv64i2p1_svnapot1p0" ; RV64SVPBMT: .attribute 5, "rv64i2p1_svpbmt1p0" -; RV64SVUKTE: .attribute 5, "rv64i2p1_svukte0p3" +; RV64SVUKTE: .attribute 5, "rv64i2p1_svukte1p0" ; RV64SVVPTC: .attribute 5, "rv64i2p1_svvptc1p0" ; RV64SVRSW60T59B: .attribute 5, "rv64i2p1_svrsw60t59b1p0" ; RV64SVINVAL: .attribute 5, "rv64i2p1_svinval1p0" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 97ca289431a4a..5f271a3db51bd 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -420,8 +420,8 @@ .attribute arch, "rv64i_svrsw60t59b1p0" # CHECK: attribute 5, "rv64i2p1_svrsw60t59b1p0" -.attribute arch, "rv32i_svukte0p3" -# CHECK: attribute 5, "rv32i2p1_svukte0p3" +.attribute arch, "rv32i_svukte1p0" +# CHECK: attribute 5, "rv32i2p1_svukte1p0" .attribute arch, "rv32i_svvptc1p0" # CHECK: attribute 5, "rv32i2p1_svvptc1p0" diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 04cbe8b9f661d..1a265e0041f9e 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1663,7 +1663,7 @@ Experimental extensions smcsps 0.19 smpmpmt 0.6 sscsps 0.19 - svukte 0.3 + svukte 1.0 xqccmt 0.1 xsfmclic 0.1 xsfsclic 0.1 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
