Author: Matt Arsenault Date: 2026-07-28T13:09:54Z New Revision: c154f4aa5483915702d8447d541d5d9a4dfaac46
URL: https://github.com/llvm/llvm-project/commit/c154f4aa5483915702d8447d541d5d9a4dfaac46 DIFF: https://github.com/llvm/llvm-project/commit/c154f4aa5483915702d8447d541d5d9a4dfaac46.diff LOG: AMDGPU: Remove dead FEATURE_FP64/FEATURE_LDEXP from ArchFeatureKind (#212479) No GPU ever sets these bits, and clang's hasFP64()/hasLDEXPF() short-circuit on isAMDGCN() before testing them, so the bits are never observed. Co-authored-by: Claude (Claude-Opus-4.8) Added: Modified: clang/lib/Basic/Targets/AMDGPU.h llvm/include/llvm/TargetParser/AMDGPUTargetParser.h Removed: ################################################################################ diff --git a/clang/lib/Basic/Targets/AMDGPU.h b/clang/lib/Basic/Targets/AMDGPU.h index 89ba561ef302d..060df0b9b1b72 100644 --- a/clang/lib/Basic/Targets/AMDGPU.h +++ b/clang/lib/Basic/Targets/AMDGPU.h @@ -50,10 +50,7 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo { llvm::StringMap<bool> OffloadArchFeatures; std::string TargetID; - bool hasFP64() const { - return getTriple().isAMDGCN() || - !!(GPUFeatures & llvm::AMDGPU::FEATURE_FP64); - } + bool hasFP64() const { return getTriple().isAMDGCN(); } /// Has fast fma f32 bool hasFastFMAF() const { @@ -72,10 +69,7 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo { return !!(GPUFeatures & llvm::AMDGPU::FEATURE_FAST_DENORMAL_F32); } - bool hasLDEXPF() const { - return getTriple().isAMDGCN() || - !!(GPUFeatures & llvm::AMDGPU::FEATURE_LDEXP); - } + bool hasLDEXPF() const { return getTriple().isAMDGCN(); } static bool isR600(const llvm::Triple &TT) { return TT.getArch() == llvm::Triple::r600; diff --git a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h b/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h index 5b35ff6b88708..bb82252803c59 100644 --- a/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h +++ b/llvm/include/llvm/TargetParser/AMDGPUTargetParser.h @@ -61,32 +61,30 @@ struct IsaVersion { enum ArchFeatureKind : uint32_t { FEATURE_NONE = 0, - // These features only exist for r600, and are implied true for amdgcn. - FEATURE_FMA = 1 << 1, - FEATURE_LDEXP = 1 << 2, - FEATURE_FP64 = 1 << 3, + // This feature only exists for r600, and is implied true for amdgcn. + FEATURE_FMA = 1 << 0, // Common features. - FEATURE_FAST_FMA_F32 = 1 << 4, - FEATURE_FAST_DENORMAL_F32 = 1 << 5, + FEATURE_FAST_FMA_F32 = 1 << 1, + FEATURE_FAST_DENORMAL_F32 = 1 << 2, // Wavefront 32 is available. - FEATURE_WAVE32 = 1 << 6, + FEATURE_WAVE32 = 1 << 3, // Xnack is available. - FEATURE_XNACK = 1 << 7, + FEATURE_XNACK = 1 << 4, // Sram-ecc is available. - FEATURE_SRAMECC = 1 << 8, + FEATURE_SRAMECC = 1 << 5, // WGP mode is supported. - FEATURE_WGP = 1 << 9, + FEATURE_WGP = 1 << 6, // Xnack on/off modes are supported. - FEATURE_XNACK_ON_OFF_MODES = 1 << 10, + FEATURE_XNACK_ON_OFF_MODES = 1 << 7, // VI SGPR initialization bug requiring a fixed SGPR allocation size. - FEATURE_SGPR_INIT_BUG = 1 << 11 + FEATURE_SGPR_INIT_BUG = 1 << 8 }; enum FeatureError : uint32_t { _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
