================
@@ -10705,33 +10707,58 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
NumVDataDwords, IsAtomicPacked16Bit, DL);
}
-SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc,
+SDValue SITargetLowering::lowerSBuffer(EVT VT, EVT MemVT, SDLoc DL,
+ SDValue Chain, SDValue Rsrc,
SDValue Offset, SDValue CachePolicy,
- SelectionDAG &DAG) const {
+ SelectionDAG &DAG,
+ MachineMemOperand *MMO) const {
MachineFunction &MF = DAG.getMachineFunction();
+ bool HasChainResult = MMO != nullptr;
- const DataLayout &DataLayout = DAG.getDataLayout();
- Align Alignment =
- DataLayout.getABITypeAlign(VT.getTypeForEVT(*DAG.getContext()));
+ if (!MMO) {
+ const DataLayout &DataLayout = DAG.getDataLayout();
+ Align Alignment =
+ DataLayout.getABITypeAlign(MemVT.getTypeForEVT(*DAG.getContext()));
- MachineMemOperand *MMO = MF.getMachineMemOperand(
- MachinePointerInfo(),
- MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable |
- MachineMemOperand::MOInvariant,
- VT.getStoreSize(), Alignment);
+ MMO = MF.getMachineMemOperand(MachinePointerInfo(),
+ MachineMemOperand::MOLoad |
+ MachineMemOperand::MODereferenceable |
+ MachineMemOperand::MOInvariant,
+ MemVT.getStoreSize(), Alignment);
+ }
if (!Offset->isDivergent()) {
- SDValue Ops[] = {Rsrc, Offset, CachePolicy};
+ SDValue Ops[] = {Chain, Rsrc, Offset, CachePolicy};
+
+ // Lower llvm.amdgcn.*s.buffer.load.(i8, u8) intrinsics. First, generate
+ // s_buffer_load_u8 for signed and unsigned load instructions. Next, DAG
+ // combiner tries to merge the s_buffer_load_u8 with a sext instruction
+ // (performSignExtendInRegCombine()) and it replaces s_buffer_load_u8 with
+ // s_buffer_load_i8.
+ if (MemVT == MVT::i8 && Subtarget->hasScalarSubwordLoads()) {
+ SDValue BufferLoad = DAG.getMemIntrinsicNode(
+ AMDGPUISD::SBUFFER_LOAD_UBYTE, DL,
+ DAG.getVTList(MVT::i32, MVT::Other), Ops, MemVT, MMO);
+ SDValue LoadVal = DAG.getAnyExtOrTrunc(
+ DAG.getNode(ISD::TRUNCATE, DL, MemVT, BufferLoad), DL, VT);
+ if (HasChainResult)
+ return DAG.getMergeValues({LoadVal, BufferLoad.getValue(1)}, DL);
+ return LoadVal;
+ }
// Lower llvm.amdgcn.s.buffer.load.{i16, u16} intrinsics. Initially, the
// s_buffer_load_u16 instruction is emitted for both signed and unsigned
// loads. Later, DAG combiner tries to combine s_buffer_load_u16 with sext
// and generates s_buffer_load_i16 (performSignExtendInRegCombine).
- if (VT == MVT::i16 && Subtarget->hasScalarSubwordLoads()) {
- SDValue BufferLoad =
- DAG.getMemIntrinsicNode(AMDGPUISD::SBUFFER_LOAD_USHORT, DL,
- DAG.getVTList(MVT::i32), Ops, VT, MMO);
- return DAG.getNode(ISD::TRUNCATE, DL, VT, BufferLoad);
+ if (MemVT == MVT::i16 && Subtarget->hasScalarSubwordLoads()) {
+ SDValue BufferLoad = DAG.getMemIntrinsicNode(
+ AMDGPUISD::SBUFFER_LOAD_USHORT, DL,
+ DAG.getVTList(MVT::i32, MVT::Other), Ops, MemVT, MMO);
+ SDValue LoadVal = DAG.getAnyExtOrTrunc(
+ DAG.getNode(ISD::TRUNCATE, DL, MemVT, BufferLoad), DL, VT);
+ if (HasChainResult)
+ return DAG.getMergeValues({LoadVal, BufferLoad.getValue(1)}, DL);
+ return LoadVal;
----------------
slinder1 wrote:
This seems unrelated to the broader change? A patch could handle `i8` here
separately, right?
It could be factored out with the existing `MVT::i16` handling?
```suggestion
// Lower llvm.amdgcn.*s.buffer.load.{i,u}* intrinsics. First, generate
// s_buffer_load_u* for signed and unsigned load instructions. Next, DAG
// combiner tries to merge the s_buffer_load_u* with a sext instruction
// (performSignExtendInRegCombine()) and it replaces s_buffer_load_u* with
// s_buffer_load_i*.
auto HandleScalarSubwordLoads = [VT, MemVT, DL, &DAG, MMO, &Ops](unsigned
Opcode) {
SDValue BufferLoad = DAG.getMemIntrinsicNode(
Opcode, DL,
DAG.getVTList(MVT::i32, MVT::Other), Ops, MemVT, MMO);
SDValue LoadVal = DAG.getAnyExtOrTrunc(
DAG.getNode(ISD::TRUNCATE, DL, MemVT, BufferLoad), DL, VT);
if (HasChainResult)
return DAG.getMergeValues({LoadVal, BufferLoad.getValue(1)}, DL);
return LoadVal;
}
if (Subtarget->hasScalarSubwordLoads()) {
if (MemVT == MVT::i8)
return HandleScalarSubwordLoads(AMDGPUISD::SBUFFER_LOAD_UBYTE);
if (MemVT == MVT::i16)
return HandleScalarSubwordLoads(AMDGPUISD::SBUFFER_LOAD_USHORT);
}
```
https://github.com/llvm/llvm-project/pull/209243
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