================
@@ -1635,6 +1635,38 @@
BuiltinTypeDeclBuilder::addByteAddressBufferStoreMethods() {
return *this;
}
+BuiltinTypeDeclBuilder &
+BuiltinTypeDeclBuilder::addByteAddressBufferInterlockedMethods() {
+ assert(!Record->isCompleteDefinition() && "record is already complete");
+ ASTContext &AST = SemaRef.getASTContext();
+
+ // Each entry declares two overloads (with and without an out original-value
+ // parameter). Adding a new atomic here only requires a new line — the shared
+ // helper takes care of the composition.
+ addByteAddressBufferInterlockedMethod("InterlockedAdd", AST.UnsignedIntTy,
+ "__builtin_hlsl_interlocked_add");
+
+ // 64-bit typed atomics on UAVs require SM 6.6 (DXIL 1.6 introduces the
+ // int64 overload of the atomicBinOp op). Skip synthesizing the *64 methods
+ // on older DXIL targets so callers get "no matching member function" from
+ // overload resolution — this matches DXC and mirrors how other HLSL SM-gated
+ // features are handled (see hlsl_intrinsics.h `_HLSL_AVAILABILITY`
+ // annotations). Non-DXIL targets (e.g., SPIR-V) always get the method: their
+ // 64-bit atomic support is gated by device extensions, not shader model.
----------------
farzonl wrote:
This comment is way to verbose and is very weird because it refrences other
sections of code that could change. If you want a comment stick to what this
part of the code is doing.
```suggestion
// Skip synthesizing the 64 bit methods on DXIL targets older that SM 6.6
```
https://github.com/llvm/llvm-project/pull/208128
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