================
@@ -11851,6 +11851,39 @@ SDValue
RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
return DAG.getNode(Opc, DL, Op.getValueType(), Op.getOperand(1),
Op.getOperand(2));
}
+ case Intrinsic::riscv_pmerge: {
+ EVT VT = Op.getValueType();
+ auto buildMerge = [&](SDValue Rs1, SDValue Rs2, SDValue Mask, EVT
ResultVT) {
+ MVT IntVT = MVT::getIntegerVT(ResultVT.getSizeInBits());
+ SDValue Res = DAG.getNode(RISCVISD::MERGE, DL, IntVT,
+ DAG.getBitcast(IntVT, Mask),
+ DAG.getBitcast(IntVT, Rs1),
+ DAG.getBitcast(IntVT, Rs2));
+ return DAG.getBitcast(ResultVT, Res);
+ };
+
+ // 64-bit packed types on RV32: split into two 32-bit halves. v2i32 has no
+ // legal 32-bit vector half, so bitcast it to v4i16 (same 64 bits) first;
+ // the merge result is identical.
+ if (!Subtarget.is64Bit() &&
+ (VT == MVT::v8i8 || VT == MVT::v4i16 || VT == MVT::v2i32)) {
+ EVT WorkVT = VT == MVT::v2i32 ? (EVT)MVT::v4i16 : VT;
----------------
topperc wrote:
```suggestion
EVT WorkVT = VT == MVT::v2i32 ? EVT(MVT::v4i16) : VT;
```
https://github.com/llvm/llvm-project/pull/207110
_______________________________________________
cfe-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
