https://github.com/zatrazz created https://github.com/llvm/llvm-project/pull/202582
This series implements three additional Microsoft `intrin.h` intrinsics in clang so MSVC-compatible code can build with clang. | Target | Intrinsic | Description | |--------|-----------|-------------| | AArch64 | `__svc` | Supervisor Call (`SVC #imm`) | | AArch64 | `__hvc` | Hypervisor Call (`HVC #imm`) | | AArch64 | `_InterlockedCompareExchangePointer_nf` | Pointer compare-and-exchange, no memory barrier (relaxed) | `__hvc` and `__svc` each require a new LLVM intrinsic (`llvm.aarch64.hvc` / `llvm.aarch64.svc`) to carry the immediate operand down to instruction selection. `_InterlockedCompareExchangePointer_nf` is the relaxed (`_nf`, "no fence") form of the existing `_InterlockedCompareExchangePointer` family and is wired up for both the ARM and AArch64 targets. These follow the MSVC semantics, where the intrinsics behave like inline assembly: the compiler emits the requested instruction directly and does not verify that the target's enabled ISA actually supports it. The `__hvc` / `__svc` immediate is range-checked as a compile-time constant (matching `cl`), but there is no feature/`-march` gating — emitting the instruction is the user's responsibility. >From a134579c0e45ffabd2835ba7cd75276f9c1b4105 Mon Sep 17 00:00:00 2001 From: Adhemerval Zanella <[email protected]> Date: Wed, 20 May 2026 10:21:07 -0300 Subject: [PATCH 1/5] [AArch64] Add _InterlockedCompareExchangePointer_nf MS intrinsic The _nf ("no fence", monotonic) variant was missing from the AArch64 target-specific builtin table. Wire the new builtin entry (BuiltinsAArch64.td) into the existing getMSVCBuiltinEquivalentIntrinsic dispatch so it resolves to MSVCIntrin::_InterlockedCompareExchange_nf, which already lowers to a monotonic volatile cmpxchg via EmitAtomicCmpXchgForMSIntrin. Documented at: https://learn.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=msvc-180 --- clang/include/clang/Basic/BuiltinsAArch64.td | 1 + clang/lib/CodeGen/TargetBuiltins/ARM.cpp | 1 + clang/test/CodeGen/ms-intrinsics.c | 8 ++++++++ 3 files changed, 10 insertions(+) diff --git a/clang/include/clang/Basic/BuiltinsAArch64.td b/clang/include/clang/Basic/BuiltinsAArch64.td index 15257f3db5b41..eefe48146035c 100644 --- a/clang/include/clang/Basic/BuiltinsAArch64.td +++ b/clang/include/clang/Basic/BuiltinsAArch64.td @@ -253,6 +253,7 @@ let Attributes = [NoThrow, RequireDeclaration], Languages = "ALL_MS_LANGUAGES", def _InterlockedCompareExchange64_nf : AArch64NoPrefixTargetLibBuiltin<"long long int (long long int volatile *, long long int, long long int)">; def _InterlockedCompareExchange64_rel : AArch64NoPrefixTargetLibBuiltin<"long long int (long long int volatile *, long long int, long long int)">; def _InterlockedCompareExchangePointer_acq : AArch64NoPrefixTargetLibBuiltin<"void * (void * volatile *, void *, void *)">; + def _InterlockedCompareExchangePointer_nf : AArch64NoPrefixTargetLibBuiltin<"void * (void * volatile *, void *, void *)">; def _InterlockedCompareExchangePointer_rel : AArch64NoPrefixTargetLibBuiltin<"void * (void * volatile *, void *, void *)">; } diff --git a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp index ece8ff21561cf..a159ed0a1ba4e 100644 --- a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp @@ -106,6 +106,7 @@ translateAarch64ToMsvcIntrin(unsigned BuiltinID) { case clang::AArch64::BI_InterlockedCompareExchange16_nf: case clang::AArch64::BI_InterlockedCompareExchange_nf: case clang::AArch64::BI_InterlockedCompareExchange64_nf: + case clang::AArch64::BI_InterlockedCompareExchangePointer_nf: return MSVCIntrin::_InterlockedCompareExchange_nf; case clang::AArch64::BI_InterlockedCompareExchange128: return MSVCIntrin::_InterlockedCompareExchange128; diff --git a/clang/test/CodeGen/ms-intrinsics.c b/clang/test/CodeGen/ms-intrinsics.c index 8b719ef8cc1fd..8e1c721ac4bc0 100644 --- a/clang/test/CodeGen/ms-intrinsics.c +++ b/clang/test/CodeGen/ms-intrinsics.c @@ -283,6 +283,14 @@ void *test_InterlockedCompareExchangePointer_nf(void * volatile *Destination, // CHECK: %[[RESULT:[0-9]+]] = inttoptr [[iPTR]] %[[EXTRACT]] to ptr // CHECK: ret ptr %[[RESULT:[0-9]+]] // CHECK: } +// CHECK-ARM64: define{{.*}}ptr @test_InterlockedCompareExchangePointer_nf(ptr {{.*}}%Destination, ptr {{[a-z_ ]*}}%Exchange, ptr {{[a-z_ ]*}}%Comparand){{.*}}{ +// CHECK-ARM64: %[[EXCHANGE:[0-9]+]] = ptrtoint ptr %Exchange to [[iPTR]] +// CHECK-ARM64: %[[COMPARAND:[0-9]+]] = ptrtoint ptr %Comparand to [[iPTR]] +// CHECK-ARM64: %[[XCHG:[0-9]+]] = cmpxchg volatile ptr %[[DEST:.+]], [[iPTR]] %[[COMPARAND:[0-9]+]], [[iPTR]] %[[EXCHANGE:[0-9]+]] monotonic monotonic, align {{4|8}} +// CHECK-ARM64: %[[EXTRACT:[0-9]+]] = extractvalue { [[iPTR]], i1 } %[[XCHG]], 0 +// CHECK-ARM64: %[[RESULT:[0-9]+]] = inttoptr [[iPTR]] %[[EXTRACT]] to ptr +// CHECK-ARM64: ret ptr %[[RESULT:[0-9]+]] +// CHECK-ARM64: } #if defined(__arm__) || defined(__aarch64__) void *test_InterlockedCompareExchangePointer_acq(void * volatile *Destination, >From a8aeb0dd570b3462a4e3d8df2dde482ba087b0a0 Mon Sep 17 00:00:00 2001 From: Adhemerval Zanella <[email protected]> Date: Thu, 4 Jun 2026 15:24:16 -0300 Subject: [PATCH 2/5] [AArch64] Add llvm.aarch64.hvc intrinsic Add a new LLVM intrinsic llvm.aarch64.hvc alongside the existing llvm.aarch64.break and llvm.aarch64.hlt, wired to the existing HVC (Hypervisor Call) instruction in the AArch64 backend. It takes a 16-bit immediate operand. Unlike hlt/break, hvc does not have IntrNoReturn since the hypervisor can return control to the caller. --- llvm/include/llvm/IR/IntrinsicsAArch64.td | 3 +++ llvm/lib/Target/AArch64/AArch64InstrInfo.td | 3 ++- llvm/test/CodeGen/AArch64/arm64-hvc.ll | 10 ++++++++++ 3 files changed, 15 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/AArch64/arm64-hvc.ll diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td index ba0d7c02bf427..190ee674f9c2f 100644 --- a/llvm/include/llvm/IR/IntrinsicsAArch64.td +++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td @@ -72,6 +72,9 @@ def int_aarch64_break : Intrinsic<[], [llvm_i32_ty], def int_aarch64_hlt : Intrinsic<[], [llvm_i32_ty], [IntrNoMem, IntrHasSideEffects, IntrNoReturn, IntrCold, ImmArg<ArgIndex<0>>]>; +def int_aarch64_hvc : Intrinsic<[], [llvm_i32_ty], + [IntrNoMem, IntrHasSideEffects, ImmArg<ArgIndex<0>>]>; + def int_aarch64_prefetch : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrInaccessibleMemOrArgMemOnly, IntrWillReturn, ReadOnly<ArgIndex<0>>, diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 200808665c93e..34b59774b0764 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -3759,7 +3759,8 @@ def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">; def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">, Requires<[HasEL3]>; def HLT : ExceptionGeneration<0b010, 0b00, "hlt", [(int_aarch64_hlt timm32_0_65535:$imm)]>; -def HVC : ExceptionGeneration<0b000, 0b10, "hvc">; +def HVC : ExceptionGeneration<0b000, 0b10, "hvc", + [(int_aarch64_hvc timm32_0_65535:$imm)]>; def SMC : ExceptionGeneration<0b000, 0b11, "smc">, Requires<[HasEL3]>; def SVC : ExceptionGeneration<0b000, 0b01, "svc">; diff --git a/llvm/test/CodeGen/AArch64/arm64-hvc.ll b/llvm/test/CodeGen/AArch64/arm64-hvc.ll new file mode 100644 index 0000000000000..14d7e22b4263f --- /dev/null +++ b/llvm/test/CodeGen/AArch64/arm64-hvc.ll @@ -0,0 +1,10 @@ +; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s + +define void @foo() nounwind { +; CHECK-LABEL: foo +; CHECK: hvc #0x2 + tail call void @llvm.aarch64.hvc(i32 2) + ret void +} + +declare void @llvm.aarch64.hvc(i32 immarg) nounwind >From e2605243eab486bd6d2148a448cc4727bee63f4c Mon Sep 17 00:00:00 2001 From: Adhemerval Zanella <[email protected]> Date: Thu, 4 Jun 2026 15:24:17 -0300 Subject: [PATCH 3/5] [AArch64] Add the __hvc MS intrinsic Add support for the __hvc MS intrinsic on AArch64, which generates an HVC (Hypervisor Call) instruction with a 16-bit immediate operand, lowered via the llvm.aarch64.hvc intrinsic. --- clang/include/clang/Basic/BuiltinsAArch64.td | 1 + clang/lib/CodeGen/TargetBuiltins/ARM.cpp | 6 ++++++ clang/lib/Headers/intrin.h | 1 + clang/lib/Sema/SemaARM.cpp | 3 +++ clang/test/CodeGen/arm64-microsoft-intrinsics.c | 10 ++++++++++ clang/test/Sema/builtins-microsoft-arm64.c | 6 ++++++ 6 files changed, 27 insertions(+) diff --git a/clang/include/clang/Basic/BuiltinsAArch64.td b/clang/include/clang/Basic/BuiltinsAArch64.td index eefe48146035c..29ef92b011f9a 100644 --- a/clang/include/clang/Basic/BuiltinsAArch64.td +++ b/clang/include/clang/Basic/BuiltinsAArch64.td @@ -409,4 +409,5 @@ let Attributes = [NoThrow, RequireDeclaration], Languages = "ALL_MS_LANGUAGES", let Attributes = [NoThrow, RequireDeclaration], Languages = "ALL_MS_LANGUAGES", Header = "intrin.h" in { def __hlt : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int, ...)">; + def __hvc : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int, ...)">; } diff --git a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp index a159ed0a1ba4e..1f22206573de7 100644 --- a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp @@ -5328,6 +5328,12 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID, return ConstantInt::get(Builder.getInt32Ty(), 0); } + if (BuiltinID == AArch64::BI__hvc) { + Function *F = CGM.getIntrinsic(Intrinsic::aarch64_hvc); + Builder.CreateCall(F, {EmitScalarExpr(E->getArg(0))}); + return ConstantInt::get(Builder.getInt32Ty(), 0); + } + if (BuiltinID == NEON::BI__builtin_neon_vcvth_bf16_f32) return Builder.CreateFPTrunc( Builder.CreateBitCast(EmitScalarExpr(E->getArg(0)), diff --git a/clang/lib/Headers/intrin.h b/clang/lib/Headers/intrin.h index 4cb8cac960bcf..f8a7cbb4f8192 100644 --- a/clang/lib/Headers/intrin.h +++ b/clang/lib/Headers/intrin.h @@ -448,6 +448,7 @@ unsigned int _CountTrailingZeros(unsigned long); unsigned int _CountTrailingZeros64(unsigned __int64); unsigned int __hlt(unsigned int, ...); +unsigned int __hvc(unsigned int, ...); void __cdecl __prefetch(const void *); void __cdecl __prefetch2(const void *, unsigned char); diff --git a/clang/lib/Sema/SemaARM.cpp b/clang/lib/Sema/SemaARM.cpp index 5e7504fab416d..edcaf1ff029c4 100644 --- a/clang/lib/Sema/SemaARM.cpp +++ b/clang/lib/Sema/SemaARM.cpp @@ -1189,6 +1189,9 @@ bool SemaARM::CheckAArch64BuiltinFunctionCall(const TargetInfo &TI, if (BuiltinID == AArch64::BI__hlt) return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 0xffff); + if (BuiltinID == AArch64::BI__hvc) + return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 0xffff); + if (CheckNeonBuiltinFunctionCall(TI, BuiltinID, TheCall)) return true; diff --git a/clang/test/CodeGen/arm64-microsoft-intrinsics.c b/clang/test/CodeGen/arm64-microsoft-intrinsics.c index e6a415a0d8805..8c51290e078b7 100644 --- a/clang/test/CodeGen/arm64-microsoft-intrinsics.c +++ b/clang/test/CodeGen/arm64-microsoft-intrinsics.c @@ -147,6 +147,16 @@ void check__hlt() { // CHECK-MSVC: call void @llvm.aarch64.hlt(i32 0) // CHECK-LINUX: error: call to undeclared function '__hlt' +void check__hvc() { + __hvc(0); + __hvc(1); +} + +// CHECK-MSVC-LABEL: define {{.*}} void @check__hvc() +// CHECK-MSVC: call void @llvm.aarch64.hvc(i32 0) +// CHECK-MSVC: call void @llvm.aarch64.hvc(i32 1) +// CHECK-LINUX: error: call to undeclared function '__hvc' + unsigned __int64 check__getReg(void) { unsigned volatile __int64 reg; reg = __getReg(18); diff --git a/clang/test/Sema/builtins-microsoft-arm64.c b/clang/test/Sema/builtins-microsoft-arm64.c index 22163ab3fa851..f2359fdf452ac 100644 --- a/clang/test/Sema/builtins-microsoft-arm64.c +++ b/clang/test/Sema/builtins-microsoft-arm64.c @@ -14,6 +14,12 @@ void check__hlt() { __hlt(65536); // expected-error-re {{argument value {{.*}} is outside the valid range}} } +void check__hvc(unsigned int x) { + __hvc(-1); // expected-error-re {{argument value {{.*}} is outside the valid range}} + __hvc(65536); // expected-error-re {{argument value {{.*}} is outside the valid range}} + __hvc(x); // expected-error {{argument to '__hvc' must be a constant integer}} +} + void check__getReg(void) { __getReg(-1); // expected-error-re {{argument value {{.*}} is outside the valid range}} __getReg(32); // expected-error-re {{argument value {{.*}} is outside the valid range}} >From 8fe07645b6432f3ec7558668378248b780784061 Mon Sep 17 00:00:00 2001 From: Adhemerval Zanella <[email protected]> Date: Thu, 28 May 2026 13:51:44 -0300 Subject: [PATCH 4/5] [AArch64] Add the llvm.aarch64.svc intrinsic Add the llvm.aarch64.svc intrinsic alongside the existing llvm.aarch64.hvc, wired to the existing SVC instruction definition in the AArch64 backend. It generates the SVC (Supervisor Call) instruction with a 16-bit immediate operand. Like hvc, svc does not have IntrNoReturn since the supervisor can return control to the caller. --- llvm/include/llvm/IR/IntrinsicsAArch64.td | 3 +++ llvm/lib/Target/AArch64/AArch64InstrInfo.td | 3 ++- llvm/test/CodeGen/AArch64/arm64-svc.ll | 10 ++++++++++ 3 files changed, 15 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/AArch64/arm64-svc.ll diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td index 190ee674f9c2f..ecccf6eddfc64 100644 --- a/llvm/include/llvm/IR/IntrinsicsAArch64.td +++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td @@ -75,6 +75,9 @@ def int_aarch64_hlt : Intrinsic<[], [llvm_i32_ty], def int_aarch64_hvc : Intrinsic<[], [llvm_i32_ty], [IntrNoMem, IntrHasSideEffects, ImmArg<ArgIndex<0>>]>; +def int_aarch64_svc : Intrinsic<[], [llvm_i32_ty], + [IntrNoMem, IntrHasSideEffects, ImmArg<ArgIndex<0>>]>; + def int_aarch64_prefetch : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrInaccessibleMemOrArgMemOnly, IntrWillReturn, ReadOnly<ArgIndex<0>>, diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 34b59774b0764..aa33c34ce7ab2 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -3762,7 +3762,8 @@ def HLT : ExceptionGeneration<0b010, 0b00, "hlt", def HVC : ExceptionGeneration<0b000, 0b10, "hvc", [(int_aarch64_hvc timm32_0_65535:$imm)]>; def SMC : ExceptionGeneration<0b000, 0b11, "smc">, Requires<[HasEL3]>; -def SVC : ExceptionGeneration<0b000, 0b01, "svc">; +def SVC : ExceptionGeneration<0b000, 0b01, "svc", + [(int_aarch64_svc timm32_0_65535:$imm)]>; // DCPSn defaults to an immediate operand of zero if unspecified. def : InstAlias<"dcps1", (DCPS1 0)>; diff --git a/llvm/test/CodeGen/AArch64/arm64-svc.ll b/llvm/test/CodeGen/AArch64/arm64-svc.ll new file mode 100644 index 0000000000000..2bb0719413429 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/arm64-svc.ll @@ -0,0 +1,10 @@ +; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s + +define void @foo() nounwind { +; CHECK-LABEL: foo +; CHECK: svc #0x2 + tail call void @llvm.aarch64.svc(i32 2) + ret void +} + +declare void @llvm.aarch64.svc(i32 immarg) nounwind >From c858f040369d7498c5808c7c59ce385006cfb249 Mon Sep 17 00:00:00 2001 From: Adhemerval Zanella <[email protected]> Date: Thu, 28 May 2026 13:52:04 -0300 Subject: [PATCH 5/5] [AArch64] Add the __svc MS intrinsic Add support for the __svc MS intrinsic on AArch64, lowering to the llvm.aarch64.svc intrinsic. It generates the SVC (Supervisor Call) instruction with a 16-bit immediate operand and mirrors the existing __hvc intrinsic. --- clang/include/clang/Basic/BuiltinsAArch64.td | 1 + clang/lib/CodeGen/TargetBuiltins/ARM.cpp | 6 ++++++ clang/lib/Headers/intrin.h | 1 + clang/lib/Sema/SemaARM.cpp | 3 +++ clang/test/CodeGen/arm64-microsoft-intrinsics.c | 10 ++++++++++ clang/test/Sema/builtins-microsoft-arm64.c | 6 ++++++ 6 files changed, 27 insertions(+) diff --git a/clang/include/clang/Basic/BuiltinsAArch64.td b/clang/include/clang/Basic/BuiltinsAArch64.td index 29ef92b011f9a..0d2e936d7b7b3 100644 --- a/clang/include/clang/Basic/BuiltinsAArch64.td +++ b/clang/include/clang/Basic/BuiltinsAArch64.td @@ -410,4 +410,5 @@ let Attributes = [NoThrow, RequireDeclaration], Languages = "ALL_MS_LANGUAGES", let Attributes = [NoThrow, RequireDeclaration], Languages = "ALL_MS_LANGUAGES", Header = "intrin.h" in { def __hlt : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int, ...)">; def __hvc : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int, ...)">; + def __svc : AArch64NoPrefixTargetLibBuiltin<"unsigned int (unsigned int, ...)">; } diff --git a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp index 1f22206573de7..00b90eee21565 100644 --- a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp @@ -5334,6 +5334,12 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID, return ConstantInt::get(Builder.getInt32Ty(), 0); } + if (BuiltinID == AArch64::BI__svc) { + Function *F = CGM.getIntrinsic(Intrinsic::aarch64_svc); + Builder.CreateCall(F, {EmitScalarExpr(E->getArg(0))}); + return ConstantInt::get(Builder.getInt32Ty(), 0); + } + if (BuiltinID == NEON::BI__builtin_neon_vcvth_bf16_f32) return Builder.CreateFPTrunc( Builder.CreateBitCast(EmitScalarExpr(E->getArg(0)), diff --git a/clang/lib/Headers/intrin.h b/clang/lib/Headers/intrin.h index f8a7cbb4f8192..7dcb5a526afb2 100644 --- a/clang/lib/Headers/intrin.h +++ b/clang/lib/Headers/intrin.h @@ -449,6 +449,7 @@ unsigned int _CountTrailingZeros64(unsigned __int64); unsigned int __hlt(unsigned int, ...); unsigned int __hvc(unsigned int, ...); +unsigned int __svc(unsigned int, ...); void __cdecl __prefetch(const void *); void __cdecl __prefetch2(const void *, unsigned char); diff --git a/clang/lib/Sema/SemaARM.cpp b/clang/lib/Sema/SemaARM.cpp index edcaf1ff029c4..664525fdb3232 100644 --- a/clang/lib/Sema/SemaARM.cpp +++ b/clang/lib/Sema/SemaARM.cpp @@ -1192,6 +1192,9 @@ bool SemaARM::CheckAArch64BuiltinFunctionCall(const TargetInfo &TI, if (BuiltinID == AArch64::BI__hvc) return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 0xffff); + if (BuiltinID == AArch64::BI__svc) + return SemaRef.BuiltinConstantArgRange(TheCall, 0, 0, 0xffff); + if (CheckNeonBuiltinFunctionCall(TI, BuiltinID, TheCall)) return true; diff --git a/clang/test/CodeGen/arm64-microsoft-intrinsics.c b/clang/test/CodeGen/arm64-microsoft-intrinsics.c index 8c51290e078b7..5bb7d1f9f4a7d 100644 --- a/clang/test/CodeGen/arm64-microsoft-intrinsics.c +++ b/clang/test/CodeGen/arm64-microsoft-intrinsics.c @@ -157,6 +157,16 @@ void check__hvc() { // CHECK-MSVC: call void @llvm.aarch64.hvc(i32 1) // CHECK-LINUX: error: call to undeclared function '__hvc' +void check__svc() { + __svc(0); + __svc(1); +} + +// CHECK-MSVC-LABEL: define {{.*}} void @check__svc() +// CHECK-MSVC: call void @llvm.aarch64.svc(i32 0) +// CHECK-MSVC: call void @llvm.aarch64.svc(i32 1) +// CHECK-LINUX: error: call to undeclared function '__svc' + unsigned __int64 check__getReg(void) { unsigned volatile __int64 reg; reg = __getReg(18); diff --git a/clang/test/Sema/builtins-microsoft-arm64.c b/clang/test/Sema/builtins-microsoft-arm64.c index f2359fdf452ac..6e07a75af9a46 100644 --- a/clang/test/Sema/builtins-microsoft-arm64.c +++ b/clang/test/Sema/builtins-microsoft-arm64.c @@ -20,6 +20,12 @@ void check__hvc(unsigned int x) { __hvc(x); // expected-error {{argument to '__hvc' must be a constant integer}} } +void check__svc(unsigned int x) { + __svc(-1); // expected-error-re {{argument value {{.*}} is outside the valid range}} + __svc(65536); // expected-error-re {{argument value {{.*}} is outside the valid range}} + __svc(x); // expected-error {{argument to '__svc' must be a constant integer}} +} + void check__getReg(void) { __getReg(-1); // expected-error-re {{argument value {{.*}} is outside the valid range}} __getReg(32); // expected-error-re {{argument value {{.*}} is outside the valid range}} _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
