https://github.com/E00N777 updated https://github.com/llvm/llvm-project/pull/191129
>From ac04c0fbb57ef7c6999efa154162a924fea1803a Mon Sep 17 00:00:00 2001 From: E0N777 <[email protected]> Date: Thu, 9 Apr 2026 15:24:43 +0800 Subject: [PATCH] [CIR][AArch64] Lower NEON vrsra_n intrinsics --- .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 65 ++++- clang/test/CodeGen/AArch64/neon-intrinsics.c | 245 ----------------- clang/test/CodeGen/AArch64/neon/intrinsics.c | 255 ++++++++++++++++++ 3 files changed, 314 insertions(+), 251 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index cd29c2f16c004..cc1324c14cfc5 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -182,13 +182,32 @@ static mlir::Value emitNeonSplat(CIRGenBuilderTy &builder, mlir::Location loc, return builder.createVecShuffle(loc, v, shuffleMask); } +/// Flip the signedness of `vecTy`'s element type, keeping the width and +/// number of lanes the same. Used when a NEON intrinsic takes a shift +/// amount vector that must be signed (e.g. aarch64.neon.urshl takes a +/// signed amount even though the data vector is unsigned). +static cir::VectorType getSignChangedVectorType(CIRGenBuilderTy &builder, + cir::VectorType vecTy) { + auto elemTy = mlir::cast<cir::IntType>(vecTy.getElementType()); + elemTy = elemTy.isSigned() ? builder.getUIntNTy(elemTy.getWidth()) + : builder.getSIntNTy(elemTy.getWidth()); + return cir::VectorType::get(elemTy, vecTy.getSize()); +} + /// Build a constant shift amount vector of `vecTy` to shift a vector /// Here `shitfVal` is a constant integer that will be broadcast into a /// a const vector of `vecTy` which is the return value of this function +/// If `neg` is true, the shift amount is negated before splatting (used +/// when encoding a right shift as a left shift by a negative amount for +/// intrinsics like aarch64.neon.{s,u}rshl). static mlir::Value emitNeonShiftVector(CIRGenBuilderTy &builder, mlir::Value shiftVal, cir::VectorType vecTy, - mlir::Location loc) { + mlir::Location loc, bool neg) { + if (neg) { + int64_t shiftAmt = -getIntValueFromConstOp(shiftVal); + shiftVal = builder.getConstantInt(loc, vecTy.getElementType(), shiftAmt); + } mlir::Type eltTy = vecTy.getElementType(); if (shiftVal.getType() != eltTy) { shiftVal = builder.createIntCast(shiftVal, eltTy); @@ -201,7 +220,7 @@ static mlir::Value emitCommonNeonShift(CIRGenBuilderTy &builder, cir::VectorType resTy, mlir::Value shifTgt, mlir::Value shiftAmt, bool shiftLeft) { - shiftAmt = emitNeonShiftVector(builder, shiftAmt, resTy, loc); + shiftAmt = emitNeonShiftVector(builder, shiftAmt, resTy, loc, /*neg=*/false); return cir::ShiftOp::create(builder, loc, resTy, builder.createBitcast(shifTgt, resTy), shiftAmt, shiftLeft); @@ -764,7 +783,9 @@ emitNeonCallToOp(CIRGenModule &cgm, CIRGenBuilderTy &builder, assert(!cir::MissingFeatures::emitConstrainedFPCall()); } if (shift > 0 && shift == j) { - cgm.errorNYI(loc, std::string("intrinsic requiring a shift Op")); + args[j] = emitNeonShiftVector(builder, args[j], + mlir::cast<cir::VectorType>(argTypes[j]), + loc, rightshift); } else { args[j] = builder.createBitcast(args[j], argTypes[j]); } @@ -2229,12 +2250,29 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, case NEON::BI__builtin_neon_vqshld_n_s64: case NEON::BI__builtin_neon_vrshrd_n_u64: case NEON::BI__builtin_neon_vrshrd_n_s64: - case NEON::BI__builtin_neon_vrsrad_n_u64: - case NEON::BI__builtin_neon_vrsrad_n_s64: cgm.errorNYI(expr->getSourceRange(), std::string("unimplemented AArch64 builtin call: ") + getContext().BuiltinInfo.getName(builtinID)); return mlir::Value{}; + case NEON::BI__builtin_neon_vrsrad_n_u64: + case NEON::BI__builtin_neon_vrsrad_n_s64: { + cir::IntType int64Type = builtinID == NEON::BI__builtin_neon_vrsrad_n_u64 + ? builder.getUInt64Ty() + : builder.getSInt64Ty(); + ops[1] = builder.createBitcast(ops[1], int64Type); + ops[2] = builder.createNeg(ops[2]); + const StringRef intrName = builtinID == NEON::BI__builtin_neon_vrsrad_n_u64 + ? "aarch64.neon.urshl" + : "aarch64.neon.srshl"; + + llvm::SmallVector<mlir::Value, 2> args = { + ops[1], builder.createIntCast(ops[2], builder.getSInt64Ty())}; + ops[1] = + emitNeonCall(cgm, builder, {int64Type, builder.getSInt64Ty()}, args, + intrName, int64Type, getLoc(expr->getExprLoc())); + return builder.createAdd(loc, ops[0], + builder.createBitcast(ops[1], int64Type)); + } case NEON::BI__builtin_neon_vshld_n_s64: case NEON::BI__builtin_neon_vshld_n_u64: { auto loc = getLoc(expr->getExprLoc()); @@ -2544,8 +2582,23 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, case NEON::BI__builtin_neon_vsliq_n_v: case NEON::BI__builtin_neon_vsra_n_v: case NEON::BI__builtin_neon_vsraq_n_v: + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AArch64 builtin call: ") + + getContext().BuiltinInfo.getName(builtinID)); + return mlir::Value{}; case NEON::BI__builtin_neon_vrsra_n_v: - case NEON::BI__builtin_neon_vrsraq_n_v: + case NEON::BI__builtin_neon_vrsraq_n_v: { + intrName = usgn ? "aarch64.neon.urshl" : "aarch64.neon.srshl"; + cir::VectorType shiftAmtVecTy = + usgn ? getSignChangedVectorType(builder, ty) : ty; + llvm::SmallVector<mlir::Value, 2> tmpOps = {ops[1], ops[2]}; + mlir::Value tmp = emitNeonCall(cgm, builder, {ty, shiftAmtVecTy}, tmpOps, + intrName, ty, loc, + /*isConstrainedFPIntrinsic=*/false, + /*shift=*/1, /*rightshift=*/true); + ops[0] = builder.createBitcast(ops[0], ty); + return builder.createAdd(loc, ops[0], tmp); + } case NEON::BI__builtin_neon_vld1_v: case NEON::BI__builtin_neon_vld1q_v: case NEON::BI__builtin_neon_vst1_v: diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c index 7c5a7336ef6b6..860f46fa241cc 100644 --- a/clang/test/CodeGen/AArch64/neon-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c @@ -6013,199 +6013,6 @@ uint64x2_t test_vrshrq_n_u64(uint64x2_t a) { return vrshrq_n_u64(a, 3); } -// CHECK-LABEL: define dso_local <8 x i8> @test_vrsra_n_s8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VRSHR_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> [[B]], <8 x i8> splat (i8 -3)) -// CHECK-NEXT: [[TMP0:%.*]] = add <8 x i8> [[A]], [[VRSHR_N]] -// CHECK-NEXT: ret <8 x i8> [[TMP0]] -// -int8x8_t test_vrsra_n_s8(int8x8_t a, int8x8_t b) { - return vrsra_n_s8(a, b, 3); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vrsra_n_s16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> [[VRSHR_N]], <4 x i16> splat (i16 -3)) -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[TMP3:%.*]] = add <4 x i16> [[TMP2]], [[VRSHR_N1]] -// CHECK-NEXT: ret <4 x i16> [[TMP3]] -// -int16x4_t test_vrsra_n_s16(int16x4_t a, int16x4_t b) { - return vrsra_n_s16(a, b, 3); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vrsra_n_s32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> -// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> [[VRSHR_N]], <2 x i32> splat (i32 -3)) -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[TMP3:%.*]] = add <2 x i32> [[TMP2]], [[VRSHR_N1]] -// CHECK-NEXT: ret <2 x i32> [[TMP3]] -// -int32x2_t test_vrsra_n_s32(int32x2_t a, int32x2_t b) { - return vrsra_n_s32(a, b, 3); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vrsraq_n_s8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VRSHR_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> [[B]], <16 x i8> splat (i8 -3)) -// CHECK-NEXT: [[TMP0:%.*]] = add <16 x i8> [[A]], [[VRSHR_N]] -// CHECK-NEXT: ret <16 x i8> [[TMP0]] -// -int8x16_t test_vrsraq_n_s8(int8x16_t a, int8x16_t b) { - return vrsraq_n_s8(a, b, 3); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vrsraq_n_s16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> -// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> -// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> [[VRSHR_N]], <8 x i16> splat (i16 -3)) -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[TMP3:%.*]] = add <8 x i16> [[TMP2]], [[VRSHR_N1]] -// CHECK-NEXT: ret <8 x i16> [[TMP3]] -// -int16x8_t test_vrsraq_n_s16(int16x8_t a, int16x8_t b) { - return vrsraq_n_s16(a, b, 3); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vrsraq_n_s32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> -// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> -// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> [[VRSHR_N]], <4 x i32> splat (i32 -3)) -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[TMP3:%.*]] = add <4 x i32> [[TMP2]], [[VRSHR_N1]] -// CHECK-NEXT: ret <4 x i32> [[TMP3]] -// -int32x4_t test_vrsraq_n_s32(int32x4_t a, int32x4_t b) { - return vrsraq_n_s32(a, b, 3); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vrsraq_n_s64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> -// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> -// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> [[VRSHR_N]], <2 x i64> splat (i64 -3)) -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[TMP3:%.*]] = add <2 x i64> [[TMP2]], [[VRSHR_N1]] -// CHECK-NEXT: ret <2 x i64> [[TMP3]] -// -int64x2_t test_vrsraq_n_s64(int64x2_t a, int64x2_t b) { - return vrsraq_n_s64(a, b, 3); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vrsra_n_u8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VRSHR_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> [[B]], <8 x i8> splat (i8 -3)) -// CHECK-NEXT: [[TMP0:%.*]] = add <8 x i8> [[A]], [[VRSHR_N]] -// CHECK-NEXT: ret <8 x i8> [[TMP0]] -// -uint8x8_t test_vrsra_n_u8(uint8x8_t a, uint8x8_t b) { - return vrsra_n_u8(a, b, 3); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vrsra_n_u16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> [[VRSHR_N]], <4 x i16> splat (i16 -3)) -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[TMP3:%.*]] = add <4 x i16> [[TMP2]], [[VRSHR_N1]] -// CHECK-NEXT: ret <4 x i16> [[TMP3]] -// -uint16x4_t test_vrsra_n_u16(uint16x4_t a, uint16x4_t b) { - return vrsra_n_u16(a, b, 3); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vrsra_n_u32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> -// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> [[VRSHR_N]], <2 x i32> splat (i32 -3)) -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[TMP3:%.*]] = add <2 x i32> [[TMP2]], [[VRSHR_N1]] -// CHECK-NEXT: ret <2 x i32> [[TMP3]] -// -uint32x2_t test_vrsra_n_u32(uint32x2_t a, uint32x2_t b) { - return vrsra_n_u32(a, b, 3); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vrsraq_n_u8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VRSHR_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> [[B]], <16 x i8> splat (i8 -3)) -// CHECK-NEXT: [[TMP0:%.*]] = add <16 x i8> [[A]], [[VRSHR_N]] -// CHECK-NEXT: ret <16 x i8> [[TMP0]] -// -uint8x16_t test_vrsraq_n_u8(uint8x16_t a, uint8x16_t b) { - return vrsraq_n_u8(a, b, 3); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vrsraq_n_u16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> -// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> -// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> [[VRSHR_N]], <8 x i16> splat (i16 -3)) -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[TMP3:%.*]] = add <8 x i16> [[TMP2]], [[VRSHR_N1]] -// CHECK-NEXT: ret <8 x i16> [[TMP3]] -// -uint16x8_t test_vrsraq_n_u16(uint16x8_t a, uint16x8_t b) { - return vrsraq_n_u16(a, b, 3); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vrsraq_n_u32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> -// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> -// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> [[VRSHR_N]], <4 x i32> splat (i32 -3)) -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[TMP3:%.*]] = add <4 x i32> [[TMP2]], [[VRSHR_N1]] -// CHECK-NEXT: ret <4 x i32> [[TMP3]] -// -uint32x4_t test_vrsraq_n_u32(uint32x4_t a, uint32x4_t b) { - return vrsraq_n_u32(a, b, 3); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vrsraq_n_u64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> -// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> -// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> [[VRSHR_N]], <2 x i64> splat (i64 -3)) -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[TMP3:%.*]] = add <2 x i64> [[TMP2]], [[VRSHR_N1]] -// CHECK-NEXT: ret <2 x i64> [[TMP3]] -// -uint64x2_t test_vrsraq_n_u64(uint64x2_t a, uint64x2_t b) { - return vrsraq_n_u64(a, b, 3); -} // CHECK-LABEL: define dso_local <8 x i8> @test_vsri_n_s8( // CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { @@ -16305,58 +16112,6 @@ uint64x1_t test_vsra_n_u64(uint64x1_t a, uint64x1_t b) { return vsra_n_u64(a, b, 1); } -// CHECK-LABEL: define dso_local i64 @test_vrsrad_n_s64( -// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.aarch64.neon.srshl.i64(i64 [[B]], i64 -63) -// CHECK-NEXT: [[TMP1:%.*]] = add i64 [[A]], [[TMP0]] -// CHECK-NEXT: ret i64 [[TMP1]] -// -int64_t test_vrsrad_n_s64(int64_t a, int64_t b) { - return (int64_t)vrsrad_n_s64(a, b, 63); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vrsra_n_s64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> -// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> -// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> [[VRSHR_N]], <1 x i64> splat (i64 -1)) -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[TMP3:%.*]] = add <1 x i64> [[TMP2]], [[VRSHR_N1]] -// CHECK-NEXT: ret <1 x i64> [[TMP3]] -// -int64x1_t test_vrsra_n_s64(int64x1_t a, int64x1_t b) { - return vrsra_n_s64(a, b, 1); -} - -// CHECK-LABEL: define dso_local i64 @test_vrsrad_n_u64( -// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.aarch64.neon.urshl.i64(i64 [[B]], i64 -63) -// CHECK-NEXT: [[TMP1:%.*]] = add i64 [[A]], [[TMP0]] -// CHECK-NEXT: ret i64 [[TMP1]] -// -uint64_t test_vrsrad_n_u64(uint64_t a, uint64_t b) { - return (uint64_t)vrsrad_n_u64(a, b, 63); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vrsra_n_u64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> -// CHECK-NEXT: [[VRSHR_N:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> -// CHECK-NEXT: [[VRSHR_N1:%.*]] = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> [[VRSHR_N]], <1 x i64> splat (i64 -1)) -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[TMP3:%.*]] = add <1 x i64> [[TMP2]], [[VRSHR_N1]] -// CHECK-NEXT: ret <1 x i64> [[TMP3]] -// -uint64x1_t test_vrsra_n_u64(uint64x1_t a, uint64x1_t b) { - return vrsra_n_u64(a, b, 1); -} - // CHECK-LABEL: define dso_local i8 @test_vqshlb_n_s8( // CHECK-SAME: i8 noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index 7d8b7c0e7b629..521b295e287d9 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -3018,3 +3018,258 @@ mfloat8x16_t test_vbslq_mf8(uint8x16_t v1, mfloat8x16_t v2, mfloat8x16_t v3) { // LLVM: ret <16 x i8> [[VBSL2_I]] return vbslq_mf8(v1, v2, v3); } + +//===------------------------------------------------------===// +// 2.1.3.2.4 Vector rounding shift right and accumulate +// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-rounding-shift-right-and-accumulate +//===------------------------------------------------------===// + +// ALL-LABEL: @test_vrsra_n_s8( +int8x8_t test_vrsra_n_s8(int8x8_t a, int8x8_t b) { + // CIR: [[C_M1:%.*]] = cir.const #cir.int<-1> : !s8i + // CIR: [[SHIFT:%.*]] = cir.vec.splat [[C_M1]] : !s8i, !cir.vector<8 x !s8i> + // CIR: [[RSH:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.srshl" %{{.*}}, [[SHIFT]] : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s8i> + // CIR: [[RES:%.*]] = cir.add %{{.*}}, [[RSH]] : !cir.vector<8 x !s8i> + + // LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]]) {{.*}} { + // LLVM: [[RSH:%.*]] = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> [[B]], <8 x i8> splat (i8 -1)) + // LLVM: [[RES:%.*]] = add <8 x i8> [[A]], [[RSH]] + // LLVM: ret <8 x i8> [[RES]] + return vrsra_n_s8(a, b, 1); +} + +// ALL-LABEL: @test_vrsraq_n_s8( +int8x16_t test_vrsraq_n_s8(int8x16_t a, int8x16_t b) { + // CIR: [[C_M1:%.*]] = cir.const #cir.int<-1> : !s8i + // CIR: [[SHIFT:%.*]] = cir.vec.splat [[C_M1]] : !s8i, !cir.vector<16 x !s8i> + // CIR: [[RSH:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.srshl" %{{.*}}, [[SHIFT]] : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>) -> !cir.vector<16 x !s8i> + // CIR: [[RES:%.*]] = cir.add %{{.*}}, [[RSH]] : !cir.vector<16 x !s8i> + + // LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]]) {{.*}} { + // LLVM: [[RSH:%.*]] = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> [[B]], <16 x i8> splat (i8 -1)) + // LLVM: [[RES:%.*]] = add <16 x i8> [[A]], [[RSH]] + // LLVM: ret <16 x i8> [[RES]] + return vrsraq_n_s8(a, b, 1); +} + +// ALL-LABEL: @test_vrsra_n_s16( +int16x4_t test_vrsra_n_s16(int16x4_t a, int16x4_t b) { + // CIR: [[C_M1:%.*]] = cir.const #cir.int<-1> : !s16i + // CIR: [[SHIFT:%.*]] = cir.vec.splat [[C_M1]] : !s16i, !cir.vector<4 x !s16i> + // CIR: [[RSH:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.srshl" %{{.*}}, [[SHIFT]] : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>) -> !cir.vector<4 x !s16i> + // CIR: [[RES:%.*]] = cir.add %{{.*}}, [[RSH]] : !cir.vector<4 x !s16i> + + // LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]]) {{.*}} { + // LLVM: [[RSH:%.*]] = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> %{{.*}}, <4 x i16> splat (i16 -1)) + // LLVM: [[RES:%.*]] = add <4 x i16> %{{.*}}, [[RSH]] + // LLVM: ret <4 x i16> [[RES]] + return vrsra_n_s16(a, b, 1); +} + +// ALL-LABEL: @test_vrsraq_n_s16( +int16x8_t test_vrsraq_n_s16(int16x8_t a, int16x8_t b) { + // CIR: [[C_M1:%.*]] = cir.const #cir.int<-1> : !s16i + // CIR: [[SHIFT:%.*]] = cir.vec.splat [[C_M1]] : !s16i, !cir.vector<8 x !s16i> + // CIR: [[RSH:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.srshl" %{{.*}}, [[SHIFT]] : (!cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>) -> !cir.vector<8 x !s16i> + // CIR: [[RES:%.*]] = cir.add %{{.*}}, [[RSH]] : !cir.vector<8 x !s16i> + + // LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]]) {{.*}} { + // LLVM: [[RSH:%.*]] = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> %{{.*}}, <8 x i16> splat (i16 -1)) + // LLVM: [[RES:%.*]] = add <8 x i16> %{{.*}}, [[RSH]] + // LLVM: ret <8 x i16> [[RES]] + return vrsraq_n_s16(a, b, 1); +} + +// ALL-LABEL: @test_vrsra_n_s32( +int32x2_t test_vrsra_n_s32(int32x2_t a, int32x2_t b) { + // CIR: [[C_M1:%.*]] = cir.const #cir.int<-1> : !s32i + // CIR: [[SHIFT:%.*]] = cir.vec.splat [[C_M1]] : !s32i, !cir.vector<2 x !s32i> + // CIR: [[RSH:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.srshl" %{{.*}}, [[SHIFT]] : (!cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>) -> !cir.vector<2 x !s32i> + // CIR: [[RES:%.*]] = cir.add %{{.*}}, [[RSH]] : !cir.vector<2 x !s32i> + + // LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]], <2 x i32> {{.*}} [[B:%.*]]) {{.*}} { + // LLVM: [[RSH:%.*]] = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> %{{.*}}, <2 x i32> splat (i32 -1)) + // LLVM: [[RES:%.*]] = add <2 x i32> %{{.*}}, [[RSH]] + // LLVM: ret <2 x i32> [[RES]] + return vrsra_n_s32(a, b, 1); +} + +// ALL-LABEL: @test_vrsraq_n_s32( +int32x4_t test_vrsraq_n_s32(int32x4_t a, int32x4_t b) { + // CIR: [[C_M1:%.*]] = cir.const #cir.int<-1> : !s32i + // CIR: [[SHIFT:%.*]] = cir.vec.splat [[C_M1]] : !s32i, !cir.vector<4 x !s32i> + // CIR: [[RSH:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.srshl" %{{.*}}, [[SHIFT]] : (!cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>) -> !cir.vector<4 x !s32i> + // CIR: [[RES:%.*]] = cir.add %{{.*}}, [[RSH]] : !cir.vector<4 x !s32i> + + // LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]], <4 x i32> {{.*}} [[B:%.*]]) {{.*}} { + // LLVM: [[RSH:%.*]] = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> %{{.*}}, <4 x i32> splat (i32 -1)) + // LLVM: [[RES:%.*]] = add <4 x i32> %{{.*}}, [[RSH]] + // LLVM: ret <4 x i32> [[RES]] + return vrsraq_n_s32(a, b, 1); +} + +// ALL-LABEL: @test_vrsra_n_s64( +int64x1_t test_vrsra_n_s64(int64x1_t a, int64x1_t b) { + // CIR: [[C_M1:%.*]] = cir.const #cir.int<-1> : !s64i + // CIR: [[SHIFT:%.*]] = cir.vec.splat [[C_M1]] : !s64i, !cir.vector<1 x !s64i> + // CIR: [[RSH:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.srshl" %{{.*}}, [[SHIFT]] : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>) -> !cir.vector<1 x !s64i> + // CIR: [[RES:%.*]] = cir.add %{{.*}}, [[RSH]] : !cir.vector<1 x !s64i> + + // LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]], <1 x i64> {{.*}} [[B:%.*]]) {{.*}} { + // LLVM: [[RSH:%.*]] = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> %{{.*}}, <1 x i64> splat (i64 -1)) + // LLVM: [[RES:%.*]] = add <1 x i64> %{{.*}}, [[RSH]] + // LLVM: ret <1 x i64> [[RES]] + return vrsra_n_s64(a, b, 1); +} + +// ALL-LABEL: @test_vrsraq_n_s64( +int64x2_t test_vrsraq_n_s64(int64x2_t a, int64x2_t b) { + // CIR: [[C_M1:%.*]] = cir.const #cir.int<-1> : !s64i + // CIR: [[SHIFT:%.*]] = cir.vec.splat [[C_M1]] : !s64i, !cir.vector<2 x !s64i> + // CIR: [[RSH:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.srshl" %{{.*}}, [[SHIFT]] : (!cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>) -> !cir.vector<2 x !s64i> + // CIR: [[RES:%.*]] = cir.add %{{.*}}, [[RSH]] : !cir.vector<2 x !s64i> + + // LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]], <2 x i64> {{.*}} [[B:%.*]]) {{.*}} { + // LLVM: [[RSH:%.*]] = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %{{.*}}, <2 x i64> splat (i64 -1)) + // LLVM: [[RES:%.*]] = add <2 x i64> %{{.*}}, [[RSH]] + // LLVM: ret <2 x i64> [[RES]] + return vrsraq_n_s64(a, b, 1); +} + +// ALL-LABEL: @test_vrsra_n_u8( +uint8x8_t test_vrsra_n_u8(uint8x8_t a, uint8x8_t b) { + // CIR: [[C_M1:%.*]] = cir.const #cir.int<-1> : !s8i + // CIR: [[SHIFT:%.*]] = cir.vec.splat [[C_M1]] : !s8i, !cir.vector<8 x !s8i> + // CIR: [[RSH:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.urshl" %{{.*}}, [[SHIFT]] : (!cir.vector<8 x !u8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !u8i> + // CIR: [[RES:%.*]] = cir.add %{{.*}}, [[RSH]] : !cir.vector<8 x !u8i> + + // LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]]) {{.*}} { + // LLVM: [[RSH:%.*]] = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> [[B]], <8 x i8> splat (i8 -1)) + // LLVM: [[RES:%.*]] = add <8 x i8> [[A]], [[RSH]] + // LLVM: ret <8 x i8> [[RES]] + return vrsra_n_u8(a, b, 1); +} + +// ALL-LABEL: @test_vrsraq_n_u8( +uint8x16_t test_vrsraq_n_u8(uint8x16_t a, uint8x16_t b) { + // CIR: [[C_M1:%.*]] = cir.const #cir.int<-1> : !s8i + // CIR: [[SHIFT:%.*]] = cir.vec.splat [[C_M1]] : !s8i, !cir.vector<16 x !s8i> + // CIR: [[RSH:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.urshl" %{{.*}}, [[SHIFT]] : (!cir.vector<16 x !u8i>, !cir.vector<16 x !s8i>) -> !cir.vector<16 x !u8i> + // CIR: [[RES:%.*]] = cir.add %{{.*}}, [[RSH]] : !cir.vector<16 x !u8i> + + // LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]]) {{.*}} { + // LLVM: [[RSH:%.*]] = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> [[B]], <16 x i8> splat (i8 -1)) + // LLVM: [[RES:%.*]] = add <16 x i8> [[A]], [[RSH]] + // LLVM: ret <16 x i8> [[RES]] + return vrsraq_n_u8(a, b, 1); +} + +// ALL-LABEL: @test_vrsra_n_u16( +uint16x4_t test_vrsra_n_u16(uint16x4_t a, uint16x4_t b) { + // CIR: [[C_M1:%.*]] = cir.const #cir.int<-1> : !s16i + // CIR: [[SHIFT:%.*]] = cir.vec.splat [[C_M1]] : !s16i, !cir.vector<4 x !s16i> + // CIR: [[RSH:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.urshl" %{{.*}}, [[SHIFT]] : (!cir.vector<4 x !u16i>, !cir.vector<4 x !s16i>) -> !cir.vector<4 x !u16i> + // CIR: [[RES:%.*]] = cir.add %{{.*}}, [[RSH]] : !cir.vector<4 x !u16i> + + // LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]]) {{.*}} { + // LLVM: [[RSH:%.*]] = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> %{{.*}}, <4 x i16> splat (i16 -1)) + // LLVM: [[RES:%.*]] = add <4 x i16> %{{.*}}, [[RSH]] + // LLVM: ret <4 x i16> [[RES]] + return vrsra_n_u16(a, b, 1); +} + +// ALL-LABEL: @test_vrsraq_n_u16( +uint16x8_t test_vrsraq_n_u16(uint16x8_t a, uint16x8_t b) { + // CIR: [[C_M1:%.*]] = cir.const #cir.int<-1> : !s16i + // CIR: [[SHIFT:%.*]] = cir.vec.splat [[C_M1]] : !s16i, !cir.vector<8 x !s16i> + // CIR: [[RSH:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.urshl" %{{.*}}, [[SHIFT]] : (!cir.vector<8 x !u16i>, !cir.vector<8 x !s16i>) -> !cir.vector<8 x !u16i> + // CIR: [[RES:%.*]] = cir.add %{{.*}}, [[RSH]] : !cir.vector<8 x !u16i> + + // LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]]) {{.*}} { + // LLVM: [[RSH:%.*]] = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> %{{.*}}, <8 x i16> splat (i16 -1)) + // LLVM: [[RES:%.*]] = add <8 x i16> %{{.*}}, [[RSH]] + // LLVM: ret <8 x i16> [[RES]] + return vrsraq_n_u16(a, b, 1); +} + +// ALL-LABEL: @test_vrsra_n_u32( +uint32x2_t test_vrsra_n_u32(uint32x2_t a, uint32x2_t b) { + // CIR: [[C_M1:%.*]] = cir.const #cir.int<-1> : !s32i + // CIR: [[SHIFT:%.*]] = cir.vec.splat [[C_M1]] : !s32i, !cir.vector<2 x !s32i> + // CIR: [[RSH:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.urshl" %{{.*}}, [[SHIFT]] : (!cir.vector<2 x !u32i>, !cir.vector<2 x !s32i>) -> !cir.vector<2 x !u32i> + // CIR: [[RES:%.*]] = cir.add %{{.*}}, [[RSH]] : !cir.vector<2 x !u32i> + + // LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]], <2 x i32> {{.*}} [[B:%.*]]) {{.*}} { + // LLVM: [[RSH:%.*]] = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> %{{.*}}, <2 x i32> splat (i32 -1)) + // LLVM: [[RES:%.*]] = add <2 x i32> %{{.*}}, [[RSH]] + // LLVM: ret <2 x i32> [[RES]] + return vrsra_n_u32(a, b, 1); +} + +// ALL-LABEL: @test_vrsraq_n_u32( +uint32x4_t test_vrsraq_n_u32(uint32x4_t a, uint32x4_t b) { + // CIR: [[C_M1:%.*]] = cir.const #cir.int<-1> : !s32i + // CIR: [[SHIFT:%.*]] = cir.vec.splat [[C_M1]] : !s32i, !cir.vector<4 x !s32i> + // CIR: [[RSH:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.urshl" %{{.*}}, [[SHIFT]] : (!cir.vector<4 x !u32i>, !cir.vector<4 x !s32i>) -> !cir.vector<4 x !u32i> + // CIR: [[RES:%.*]] = cir.add %{{.*}}, [[RSH]] : !cir.vector<4 x !u32i> + + // LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]], <4 x i32> {{.*}} [[B:%.*]]) {{.*}} { + // LLVM: [[RSH:%.*]] = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> %{{.*}}, <4 x i32> splat (i32 -1)) + // LLVM: [[RES:%.*]] = add <4 x i32> %{{.*}}, [[RSH]] + // LLVM: ret <4 x i32> [[RES]] + return vrsraq_n_u32(a, b, 1); +} + +// ALL-LABEL: @test_vrsra_n_u64( +uint64x1_t test_vrsra_n_u64(uint64x1_t a, uint64x1_t b) { + // CIR: [[C_M1:%.*]] = cir.const #cir.int<-1> : !s64i + // CIR: [[SHIFT:%.*]] = cir.vec.splat [[C_M1]] : !s64i, !cir.vector<1 x !s64i> + // CIR: [[RSH:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.urshl" %{{.*}}, [[SHIFT]] : (!cir.vector<1 x !u64i>, !cir.vector<1 x !s64i>) -> !cir.vector<1 x !u64i> + // CIR: [[RES:%.*]] = cir.add %{{.*}}, [[RSH]] : !cir.vector<1 x !u64i> + + // LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]], <1 x i64> {{.*}} [[B:%.*]]) {{.*}} { + // LLVM: [[RSH:%.*]] = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> %{{.*}}, <1 x i64> splat (i64 -1)) + // LLVM: [[RES:%.*]] = add <1 x i64> %{{.*}}, [[RSH]] + // LLVM: ret <1 x i64> [[RES]] + return vrsra_n_u64(a, b, 1); +} + +// ALL-LABEL: @test_vrsraq_n_u64( +uint64x2_t test_vrsraq_n_u64(uint64x2_t a, uint64x2_t b) { + // CIR: [[C_M1:%.*]] = cir.const #cir.int<-1> : !s64i + // CIR: [[SHIFT:%.*]] = cir.vec.splat [[C_M1]] : !s64i, !cir.vector<2 x !s64i> + // CIR: [[RSH:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.urshl" %{{.*}}, [[SHIFT]] : (!cir.vector<2 x !u64i>, !cir.vector<2 x !s64i>) -> !cir.vector<2 x !u64i> + // CIR: [[RES:%.*]] = cir.add %{{.*}}, [[RSH]] : !cir.vector<2 x !u64i> + + // LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]], <2 x i64> {{.*}} [[B:%.*]]) {{.*}} { + // LLVM: [[RSH:%.*]] = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %{{.*}}, <2 x i64> splat (i64 -1)) + // LLVM: [[RES:%.*]] = add <2 x i64> %{{.*}}, [[RSH]] + // LLVM: ret <2 x i64> [[RES]] + return vrsraq_n_u64(a, b, 1); +} + +// ALL-LABEL: @test_vrsrad_n_s64( +int64_t test_vrsrad_n_s64(int64_t a, int64_t b) { + // CIR: [[SHIFT:%.*]] = cir.const #cir.int<-63> : !s64i + // CIR: [[RSH:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.srshl" %{{.*}}, [[SHIFT]] : (!s64i, !s64i) -> !s64i + // CIR: [[RES:%.*]] = cir.add %{{.*}}, [[RSH]] : !s64i + + // LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) {{.*}} { + // LLVM: [[RSH:%.*]] = call i64 @llvm.aarch64.neon.srshl.i64(i64 [[B]], i64 -63) + // LLVM: [[RES:%.*]] = add i64 [[A]], [[RSH]] + // LLVM: ret i64 [[RES]] + return (int64_t)vrsrad_n_s64(a, b, 63); +} + +// ALL-LABEL: @test_vrsrad_n_u64( +uint64_t test_vrsrad_n_u64(uint64_t a, uint64_t b) { + // CIR: [[SHIFT:%.*]] = cir.const #cir.int<-63> : !s64i + // CIR: [[RSH:%.*]] = cir.call_llvm_intrinsic "aarch64.neon.urshl" %{{.*}}, [[SHIFT]] : (!u64i, !s64i) -> !u64i + // CIR: [[RES:%.*]] = cir.add %{{.*}}, [[RSH]] : !u64i + + // LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) {{.*}} { + // LLVM: [[RSH:%.*]] = call i64 @llvm.aarch64.neon.urshl.i64(i64 [[B]], i64 -63) + // LLVM: [[RES:%.*]] = add i64 [[A]], [[RSH]] + // LLVM: ret i64 [[RES]] + return (uint64_t)vrsrad_n_u64(a, b, 63); +} _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
