github-actions[bot] wrote:
<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
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<details>
<summary>
You can test this locally with the following command:
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``````````bash
git-clang-format --diff origin/main HEAD --extensions h,cpp --
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.h --diff_from_common_commit
``````````
:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:
</details>
<details>
<summary>
View the diff from clang-format here.
</summary>
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 1fb7c48e3..36f323d2a 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -16953,10 +16953,10 @@ SDValue SITargetLowering::performSatAddCombine(SDNode
*N,
if (!Src1)
break;
- auto IterIsSigned = checkDot4MulSignedness(
- TempNode.getOperand(MulIdx), *Src0, *Src1,
- TempNode.getOperand(MulIdx).getOperand(0),
- TempNode.getOperand(MulIdx).getOperand(1), DAG);
+ auto IterIsSigned =
+ checkDot4MulSignedness(TempNode.getOperand(MulIdx), *Src0, *Src1,
+ TempNode.getOperand(MulIdx).getOperand(0),
+ TempNode.getOperand(MulIdx).getOperand(1), DAG);
if (!IterIsSigned)
break;
if (!MulIsSigned)
@@ -16970,12 +16970,10 @@ SDValue SITargetLowering::performSatAddCombine(SDNode
*N,
// add (mul24, mul24).
if (I == 2 && isMul(TempNode.getOperand(AddIdx))) {
Src2s.push_back(TempNode.getOperand(AddIdx));
- auto Src0 =
- handleMulOperand(TempNode.getOperand(AddIdx).getOperand(0));
+ auto Src0 = handleMulOperand(TempNode.getOperand(AddIdx).getOperand(0));
if (!Src0)
break;
- auto Src1 =
- handleMulOperand(TempNode.getOperand(AddIdx).getOperand(1));
+ auto Src1 = handleMulOperand(TempNode.getOperand(AddIdx).getOperand(1));
if (!Src1)
break;
auto IterIsSigned = checkDot4MulSignedness(
@@ -17040,13 +17038,13 @@ SDValue SITargetLowering::performSatAddCombine(SDNode
*N,
getDWordFromOffset(DAG, SL, FirstElt->SrcOp, FirstElt->DWordOffset);
auto *SecondElt = Src1s.begin();
- auto SecondEltOp = getDWordFromOffset(DAG, SL, SecondElt->SrcOp,
- SecondElt->DWordOffset);
+ auto SecondEltOp =
+ getDWordFromOffset(DAG, SL, SecondElt->SrcOp,
SecondElt->DWordOffset);
- Src0 = DAG.getBitcastedAnyExtOrTrunc(FirstEltOp, SL,
- MVT::getIntegerVT(32));
- Src1 = DAG.getBitcastedAnyExtOrTrunc(SecondEltOp, SL,
- MVT::getIntegerVT(32));
+ Src0 =
+ DAG.getBitcastedAnyExtOrTrunc(FirstEltOp, SL, MVT::getIntegerVT(32));
+ Src1 =
+ DAG.getBitcastedAnyExtOrTrunc(SecondEltOp, SL,
MVT::getIntegerVT(32));
}
}
@@ -17059,12 +17057,12 @@ SDValue SITargetLowering::performSatAddCombine(SDNode
*N,
SDValue Src2 = DAG.getExtOrTrunc(IsSigned, Accum, SL, MVT::i32);
SDValue IID = DAG.getTargetConstant(IsSigned ? Intrinsic::amdgcn_sdot4
- : Intrinsic::amdgcn_udot4,
+ : Intrinsic::amdgcn_udot4,
SL, MVT::i64);
// Generate dot4 with clamp=1 for saturation
- auto Dot = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SL, MVT::i32, IID, Src0,
- Src1, Src2, DAG.getTargetConstant(1, SL, MVT::i1));
+ auto Dot = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SL, MVT::i32, IID, Src0,
Src1,
+ Src2, DAG.getTargetConstant(1, SL, MVT::i1));
return DAG.getExtOrTrunc(IsSigned, Dot, SL, VT);
}
``````````
</details>
https://github.com/llvm/llvm-project/pull/187945
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