Author: Min-Yih Hsu Date: 2026-03-15T17:18:08-07:00 New Revision: 4c5b1c4e968270861d8acae6443a5da11df5b8d3
URL: https://github.com/llvm/llvm-project/commit/4c5b1c4e968270861d8acae6443a5da11df5b8d3 DIFF: https://github.com/llvm/llvm-project/commit/4c5b1c4e968270861d8acae6443a5da11df5b8d3.diff LOG: [RISCV] Add `sifive-x160` and `sifive-x180` processor definitions (#186264) This PR adds new processor definitions for two SiFive cores: - X160 (https://www.sifive.com/document-file/sifive-intelligence-x160-gen2-product-brief): A RV32 core with Zve32f - X180 (https://www.sifive.com/document-file/sifive-intelligence-x180-gen2-product-brief): A RVV-capable RV64 core Both of them have VLEN=128. Scheduling model supports will be added in follow-up patches. Added: clang/test/Driver/print-enabled-extensions/riscv-sifive-x160.c clang/test/Driver/print-enabled-extensions/riscv-sifive-x180.c Modified: clang/test/Driver/riscv-cpus.c clang/test/Misc/target-invalid-cpu-note/riscv.c llvm/docs/ReleaseNotes.md llvm/lib/Target/RISCV/RISCVProcessors.td Removed: ################################################################################ diff --git a/clang/test/Driver/print-enabled-extensions/riscv-sifive-x160.c b/clang/test/Driver/print-enabled-extensions/riscv-sifive-x160.c new file mode 100644 index 0000000000000..814c4f4528564 --- /dev/null +++ b/clang/test/Driver/print-enabled-extensions/riscv-sifive-x160.c @@ -0,0 +1,59 @@ +// REQUIRES: riscv-registered-target +// RUN: %clang --target=riscv32 -mcpu=sifive-x160 -menable-experimental-extensions --print-enabled-extensions | FileCheck %s + +// CHECK: Name Version Description +// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set) +// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division) +// CHECK-NEXT: a 2.1 'A' (Atomic Instructions) +// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point) +// CHECK-NEXT: c 2.0 'C' (Compressed Instructions) +// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions) +// CHECK-NEXT: zicbom 1.0 'Zicbom' (Cache-Block Management Instructions) +// CHECK-NEXT: zicbop 1.0 'Zicbop' (Cache-Block Prefetch Instructions) +// CHECK-NEXT: zicboz 1.0 'Zicboz' (Cache-Block Zero Instructions) +// CHECK-NEXT: zicond 1.0 'Zicond' (Integer Conditional Operations) +// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs) +// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i) +// CHECK-NEXT: zihintntl 1.0 'Zihintntl' (Non-Temporal Locality Hints) +// CHECK-NEXT: zihintpause 2.0 'Zihintpause' (Pause Hint) +// CHECK-NEXT: zihpm 2.0 'Zihpm' (Hardware Performance Counters) +// CHECK-NEXT: zimop 1.0 'Zimop' (May-Be-Operations) +// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication) +// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations) +// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional) +// CHECK-NEXT: zawrs 1.0 'Zawrs' (Wait on Reservation Set) +// CHECK-NEXT: zfa 1.0 'Zfa' (Additional Floating-Point) +// CHECK-NEXT: zfbfmin 1.0 'Zfbfmin' (Scalar BF16 Converts) +// CHECK-NEXT: zfh 1.0 'Zfh' (Half-Precision Floating-Point) +// CHECK-NEXT: zfhmin 1.0 'Zfhmin' (Half-Precision Floating-Point Minimal) +// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores) +// CHECK-NEXT: zcb 1.0 'Zcb' (Compressed basic bit manipulation instructions) +// CHECK-NEXT: zce 1.0 'Zce' (Compressed extensions for microcontrollers) +// CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions) +// CHECK-NEXT: zcmop 1.0 'Zcmop' (Compressed May-Be-Operations) +// CHECK-NEXT: zcmp 1.0 'Zcmp' (sequenced instructions for code-size reduction) +// CHECK-NEXT: zcmt 1.0 'Zcmt' (table jump instructions for code-size reduction) +// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) +// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) +// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) +// CHECK-NEXT: zkt 1.0 'Zkt' (Data Independent Execution Latency) +// CHECK-NEXT: zvbb 1.0 'Zvbb' (Vector basic bit-manipulation instructions) +// CHECK-NEXT: zve32f 1.0 'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension) +// CHECK-NEXT: zve32x 1.0 'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW) +// CHECK-NEXT: zvfbfmin 1.0 'Zvfbfmin' (Vector BF16 Converts) +// CHECK-NEXT: zvfbfwma 1.0 'Zvfbfwma' (Vector BF16 widening mul-add) +// CHECK-NEXT: zvfh 1.0 'Zvfh' (Vector Half-Precision Floating-Point) +// CHECK-NEXT: zvfhmin 1.0 'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) +// CHECK-NEXT: zvkb 1.0 'Zvkb' (Vector Bit-manipulation used in Cryptography) +// CHECK-NEXT: zvkt 1.0 'Zvkt' (Vector Data-Independent Execution Latency) +// CHECK-NEXT: zvl128b 1.0 'Zvl128b' (Minimum Vector Length 128) +// CHECK-NEXT: zvl32b 1.0 'Zvl32b' (Minimum Vector Length 32) +// CHECK-NEXT: zvl64b 1.0 'Zvl64b' (Minimum Vector Length 64) +// CHECK-NEXT: xsfcease 1.0 'XSfcease' (SiFive sf.cease Instruction) +// CHECK-EMPTY: +// CHECK-NEXT: Experimental extensions +// CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad) +// CHECK-NEXT: zvdot4a8i 0.1 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers) +// CHECK-NEXT: zvfbfa 0.1 'Zvfbfa' (Additional BF16 vector compute support) +// CHECK-EMPTY: +// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_c2p0_b1p0_zicbom1p0_zicbop1p0_zicboz1p0_zicfilp1p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfbfmin1p0_zfh1p0_zfhmin1p0_zca1p0_zcb1p0_zce1p0_zcf1p0_zcmop1p0_zcmp1p0_zcmt1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zvdot4a8i0p1_zve32f1p0_zve32x1p0_zvfbfa0p1_zvfbfmin1p0_zvfbfwma1p0_zvfh1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfcease1p0 diff --git a/clang/test/Driver/print-enabled-extensions/riscv-sifive-x180.c b/clang/test/Driver/print-enabled-extensions/riscv-sifive-x180.c new file mode 100644 index 0000000000000..1e992dd610682 --- /dev/null +++ b/clang/test/Driver/print-enabled-extensions/riscv-sifive-x180.c @@ -0,0 +1,71 @@ +// REQUIRES: riscv-registered-target +// RUN: %clang --target=riscv64 -mcpu=sifive-x180 -menable-experimental-extensions --print-enabled-extensions | FileCheck %s + +// CHECK: Name Version Description +// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set) +// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division) +// CHECK-NEXT: a 2.1 'A' (Atomic Instructions) +// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point) +// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point) +// CHECK-NEXT: c 2.0 'C' (Compressed Instructions) +// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions) +// CHECK-NEXT: v 1.0 'V' (Vector Extension for Application Processors) +// CHECK-NEXT: zic64b 1.0 'Zic64b' (Cache Block Size Is 64 Bytes) +// CHECK-NEXT: zicbom 1.0 'Zicbom' (Cache-Block Management Instructions) +// CHECK-NEXT: zicbop 1.0 'Zicbop' (Cache-Block Prefetch Instructions) +// CHECK-NEXT: zicboz 1.0 'Zicboz' (Cache-Block Zero Instructions) +// CHECK-NEXT: ziccamoa 1.0 'Ziccamoa' (Main Memory Supports All Atomics in A) +// CHECK-NEXT: ziccif 1.0 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement) +// CHECK-NEXT: ziccrse 1.0 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences) +// CHECK-NEXT: zicond 1.0 'Zicond' (Integer Conditional Operations) +// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs) +// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i) +// CHECK-NEXT: zihintntl 1.0 'Zihintntl' (Non-Temporal Locality Hints) +// CHECK-NEXT: zihintpause 2.0 'Zihintpause' (Pause Hint) +// CHECK-NEXT: zihpm 2.0 'Zihpm' (Hardware Performance Counters) +// CHECK-NEXT: zimop 1.0 'Zimop' (May-Be-Operations) +// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication) +// CHECK-NEXT: za64rs 1.0 'Za64rs' (Reservation Set Size of at Most 64 Bytes) +// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations) +// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional) +// CHECK-NEXT: zawrs 1.0 'Zawrs' (Wait on Reservation Set) +// CHECK-NEXT: zfa 1.0 'Zfa' (Additional Floating-Point) +// CHECK-NEXT: zfbfmin 1.0 'Zfbfmin' (Scalar BF16 Converts) +// CHECK-NEXT: zfh 1.0 'Zfh' (Half-Precision Floating-Point) +// CHECK-NEXT: zfhmin 1.0 'Zfhmin' (Half-Precision Floating-Point Minimal) +// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores) +// CHECK-NEXT: zcb 1.0 'Zcb' (Compressed basic bit manipulation instructions) +// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions) +// CHECK-NEXT: zcmop 1.0 'Zcmop' (Compressed May-Be-Operations) +// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) +// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) +// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) +// CHECK-NEXT: zkt 1.0 'Zkt' (Data Independent Execution Latency) +// CHECK-NEXT: zvbb 1.0 'Zvbb' (Vector basic bit-manipulation instructions) +// CHECK-NEXT: zve32f 1.0 'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension) +// CHECK-NEXT: zve32x 1.0 'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW) +// CHECK-NEXT: zve64d 1.0 'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension) +// CHECK-NEXT: zve64f 1.0 'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension) +// CHECK-NEXT: zve64x 1.0 'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW) +// CHECK-NEXT: zvfbfmin 1.0 'Zvfbfmin' (Vector BF16 Converts) +// CHECK-NEXT: zvfbfwma 1.0 'Zvfbfwma' (Vector BF16 widening mul-add) +// CHECK-NEXT: zvfh 1.0 'Zvfh' (Vector Half-Precision Floating-Point) +// CHECK-NEXT: zvfhmin 1.0 'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) +// CHECK-NEXT: zvkb 1.0 'Zvkb' (Vector Bit-manipulation used in Cryptography) +// CHECK-NEXT: zvkt 1.0 'Zvkt' (Vector Data-Independent Execution Latency) +// CHECK-NEXT: zvl128b 1.0 'Zvl128b' (Minimum Vector Length 128) +// CHECK-NEXT: zvl32b 1.0 'Zvl32b' (Minimum Vector Length 32) +// CHECK-NEXT: zvl64b 1.0 'Zvl64b' (Minimum Vector Length 64) +// CHECK-NEXT: xsfcease 1.0 'XSfcease' (SiFive sf.cease Instruction) +// CHECK-NEXT: xsfvfbfexp16e 0.5 'XSfvfbfexp16e' (SiFive Vector Floating-Point Exponential Function Instruction, BFloat16) +// CHECK-NEXT: xsfvfexp16e 0.5 'XSfvfexp16e' (SiFive Vector Floating-Point Exponential Function Instruction, Half Precision) +// CHECK-NEXT: xsfvfexp32e 0.5 'XSfvfexp32e' (SiFive Vector Floating-Point Exponential Function Instruction, Single Precision) +// CHECK-NEXT: xsfvfexpa 0.2 'XSfvfexpa' (SiFive Vector Floating-Point Exponential Approximation Instruction) +// CHECK-NEXT: xsifivecflushdlone 1.0 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction) +// CHECK-EMPTY: +// CHECK-NEXT: Experimental extensions +// CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad) +// CHECK-NEXT: zvdot4a8i 0.1 'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers) +// CHECK-NEXT: zvfbfa 0.1 'Zvfbfa' (Additional BF16 vector compute support) +// CHECK-EMPTY: +// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_ziccrse1p0_zicfilp1p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfbfmin1p0_zfh1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zvdot4a8i0p1_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfa0p1_zvfbfmin1p0_zvfbfwma1p0_zvfh1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfcease1p0_xsfvfbfexp16e0p5_xsfvfexp16e0p5_xsfvfexp32e0p5_xsfvfexpa0p2_xsifivecflushdlone1p0 diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index e33512a3d66aa..5ca33d91452e0 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -422,6 +422,16 @@ // COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-sifive-x390.c` // MCPU-SIFIVE-X390-SAME: "-target-abi" "lp64d" +// RUN: %clang -target riscv32 -### -c %s 2>&1 -menable-experimental-extensions -mcpu=sifive-x160 | FileCheck -check-prefix=MCPU-SIFIVE-X160 %s +// MCPU-SIFIVE-X160: "-target-cpu" "sifive-x160" +// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-sifive-x160.c` +// MCPU-SIFIVE-X160-SAME: "-target-abi" "ilp32f" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -menable-experimental-extensions -mcpu=sifive-x180 | FileCheck -check-prefix=MCPU-SIFIVE-X180 %s +// MCPU-SIFIVE-X180: "-target-cpu" "sifive-x180" +// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-sifive-x180.c` +// MCPU-SIFIVE-X180-SAME: "-target-abi" "lp64d" + // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p450 | FileCheck -check-prefix=MCPU-SIFIVE-P450 %s // MCPU-SIFIVE-P450: "-nostdsysteminc" "-target-cpu" "sifive-p450" // MCPU-SIFIVE-P450-SAME: "-target-feature" "+m" diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c index 07513c0a5bc6b..5223d1f968b8f 100644 --- a/clang/test/Misc/target-invalid-cpu-note/riscv.c +++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c @@ -17,6 +17,7 @@ // RISCV32-SAME: {{^}}, sifive-e31 // RISCV32-SAME: {{^}}, sifive-e34 // RISCV32-SAME: {{^}}, sifive-e76 +// RISCV32-SAME: {{^}}, sifive-x160 // RISCV32-SAME: {{^}}, syntacore-scr1-base // RISCV32-SAME: {{^}}, syntacore-scr1-max // RISCV32-SAME: {{^}}, syntacore-scr3-rv32 @@ -47,6 +48,7 @@ // RISCV64-SAME: {{^}}, sifive-s76 // RISCV64-SAME: {{^}}, sifive-u54 // RISCV64-SAME: {{^}}, sifive-u74 +// RISCV64-SAME: {{^}}, sifive-x180 // RISCV64-SAME: {{^}}, sifive-x280 // RISCV64-SAME: {{^}}, sifive-x390 // RISCV64-SAME: {{^}}, spacemit-a100 @@ -79,6 +81,7 @@ // TUNE-RISCV32-SAME: {{^}}, sifive-e31 // TUNE-RISCV32-SAME: {{^}}, sifive-e34 // TUNE-RISCV32-SAME: {{^}}, sifive-e76 +// TUNE-RISCV32-SAME: {{^}}, sifive-x160 // TUNE-RISCV32-SAME: {{^}}, syntacore-scr1-base // TUNE-RISCV32-SAME: {{^}}, syntacore-scr1-max // TUNE-RISCV32-SAME: {{^}}, syntacore-scr3-rv32 @@ -114,6 +117,7 @@ // TUNE-RISCV64-SAME: {{^}}, sifive-s76 // TUNE-RISCV64-SAME: {{^}}, sifive-u54 // TUNE-RISCV64-SAME: {{^}}, sifive-u74 +// TUNE-RISCV64-SAME: {{^}}, sifive-x180 // TUNE-RISCV64-SAME: {{^}}, sifive-x280 // TUNE-RISCV64-SAME: {{^}}, sifive-x390 // TUNE-RISCV64-SAME: {{^}}, spacemit-a100 diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index b1196e9720451..e685660195bcd 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -166,6 +166,7 @@ Changes to the RISC-V Backend * `-mcpu=xt-c910v2` and `-mcpu=xt-c920v2` were added. * Adds experimental assembler support for the 'Zvzip` (RISC-V Vector Reordering Structured Data) extension. +* `-mcpu=sifive-x160` and `-mcpu=sifive-x180` were added. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index bc376c4940d22..99dcc05db105a 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -350,6 +350,100 @@ def SIFIVE_X390 : RISCVProcessorModel<"sifive-x390", let ConfigurableTuneFeatures = [TuneHasSingleElementVecFP64]; } +def SIFIVE_X160 : RISCVProcessorModel<"sifive-x160", + NoSchedModel, + [Feature32Bit, + FeatureStdExtI, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtC, + FeatureStdExtB, + FeatureStdExtZicbom, + FeatureStdExtZicbop, + FeatureStdExtZicboz, + FeatureStdExtZicond, + FeatureStdExtZifencei, + FeatureStdExtZihintntl, + FeatureStdExtZihintpause, + FeatureStdExtZihpm, + FeatureStdExtZimop, + FeatureStdExtZawrs, + FeatureStdExtZfa, + FeatureStdExtZfbfmin, + FeatureStdExtZfh, + FeatureStdExtZcb, + FeatureStdExtZce, + FeatureStdExtZcf, + FeatureStdExtZcmop, + FeatureStdExtZcmp, + FeatureStdExtZcmt, + FeatureStdExtZkt, + FeatureStdExtZvbb, + FeatureStdExtZve32f, + FeatureStdExtZve32x, + FeatureStdExtZvfbfmin, + FeatureStdExtZvfbfwma, + FeatureStdExtZvfh, + FeatureStdExtZvkt, + FeatureStdExtZvl128b, + FeatureVendorXSfcease, + FeatureStdExtZicfilp, + FeatureStdExtZvdot4a8i, + FeatureStdExtZvfbfa], + SiFiveIntelligenceTuneFeatures>; + +def SIFIVE_X180 : RISCVProcessorModel<"sifive-x180", + NoSchedModel, + [Feature64Bit, + FeatureStdExtI, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtB, + FeatureStdExtV, + FeatureStdExtZic64b, + FeatureStdExtZicbom, + FeatureStdExtZicbop, + FeatureStdExtZicboz, + FeatureStdExtZiccamoa, + FeatureStdExtZiccif, + FeatureStdExtZiccrse, + FeatureStdExtZicond, + FeatureStdExtZifencei, + FeatureStdExtZihintntl, + FeatureStdExtZihintpause, + FeatureStdExtZihpm, + FeatureStdExtZimop, + FeatureStdExtZa64rs, + FeatureStdExtZawrs, + FeatureStdExtZfa, + FeatureStdExtZfbfmin, + FeatureStdExtZfh, + FeatureStdExtZcb, + FeatureStdExtZcd, + FeatureStdExtZcmop, + FeatureStdExtZkt, + FeatureStdExtZvbb, + FeatureStdExtZvfbfmin, + FeatureStdExtZvfbfwma, + FeatureStdExtZvfh, + FeatureStdExtZvkb, + FeatureStdExtZvkt, + FeatureStdExtZvl128b, + FeatureVendorXSfcease, + FeatureVendorXSfvfbfexp16e, + FeatureVendorXSfvfexp16e, + FeatureVendorXSfvfexp32e, + FeatureVendorXSfvfexpa, + FeatureVendorXSiFivecflushdlone, + FeatureStdExtZicfilp, + FeatureStdExtZvdot4a8i, + FeatureStdExtZvfbfa], + SiFiveIntelligenceTuneFeatures>; + defvar SiFiveP400TuneFeatures = [TuneNoDefaultUnroll, TuneConditionalCompressedMoveFusion, TuneLUIADDIFusion, _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
