================
@@ -90,18 +103,45 @@ void UseStdBitCheck::check(const MatchFinder::MatchResult
&Result) {
const ASTContext &Context = *Result.Context;
const SourceManager &Source = Context.getSourceManager();
- const auto *MatchedVarDecl = Result.Nodes.getNodeAs<VarDecl>("v");
- const auto *MatchedExpr = Result.Nodes.getNodeAs<BinaryOperator>("expr");
-
- auto Diag =
- diag(MatchedExpr->getBeginLoc(), "use 'std::has_one_bit' instead");
- if (auto R = MatchedExpr->getSourceRange();
- !R.getBegin().isMacroID() && !R.getEnd().isMacroID()) {
- Diag << FixItHint::CreateReplacement(
- MatchedExpr->getSourceRange(),
- ("std::has_one_bit(" + MatchedVarDecl->getName() + ")").str())
- << IncludeInserter.createIncludeInsertion(
- Source.getFileID(MatchedExpr->getBeginLoc()), "<bit>");
+ if (const auto *MatchedExpr =
+ Result.Nodes.getNodeAs<BinaryOperator>("has_one_bit_expr")) {
+ const auto *MatchedVarDecl = Result.Nodes.getNodeAs<VarDecl>("v");
+
+ auto Diag =
+ diag(MatchedExpr->getBeginLoc(), "use 'std::has_one_bit' instead");
+ if (auto R = MatchedExpr->getSourceRange();
+ !R.getBegin().isMacroID() && !R.getEnd().isMacroID()) {
+ Diag << FixItHint::CreateReplacement(
+ MatchedExpr->getSourceRange(),
+ ("std::has_one_bit(" + MatchedVarDecl->getName() +
")").str())
+ << IncludeInserter.createIncludeInsertion(
+ Source.getFileID(MatchedExpr->getBeginLoc()), "<bit>");
+ }
+ } else if (const auto *MatchedExpr =
+ Result.Nodes.getNodeAs<CXXMemberCallExpr>("popcount_expr")) {
+ const auto *BitsetInstantiatedDecl =
+ cast<ClassTemplateSpecializationDecl>(MatchedExpr->getRecordDecl());
+ const llvm::APSInt BitsetSize =
+ BitsetInstantiatedDecl->getTemplateArgs()[0].getAsIntegral();
+ const auto *MatchedArg = Result.Nodes.getNodeAs<Expr>("v");
+ const uint64_t MatchedVarSize = Context.getTypeSize(MatchedArg->getType());
+ if (BitsetSize >= MatchedVarSize) {
----------------
localspook wrote:
Prefer early return, to reduce the level of nesting:
```cpp
if (BitsetSize < MatchedVarSize)
return;
...
```
https://github.com/llvm/llvm-project/pull/185740
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