llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-llvm-ir Author: Brandon Wu (4vtomat) <details> <summary>Changes</summary> intrinsic spec PR: https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/422 --- Patch is 600.66 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/184089.diff 35 Files Affected: - (modified) clang/include/clang/Basic/riscv_vector.td (+8-8) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vv.c (+35-35) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vx.c (+30-30) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4su_vv.c (+35-35) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4su_vx.c (+30-30) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4u_vv.c (+35-35) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4u_vx.c (+30-30) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4us_vx.c (+30-30) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4_vv.c (+35-35) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4_vx.c (+30-30) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4su_vv.c (+35-35) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4su_vx.c (+30-30) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4u_vv.c (+35-35) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4u_vx.c (+30-30) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4us_vx.c (+30-30) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4_vv.c (+73-73) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4_vx.c (+60-60) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4su_vv.c (+75-75) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4su_vx.c (+60-60) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4u_vv.c (+67-67) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4u_vx.c (+60-60) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4us_vx.c (+60-60) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4_vv.c (+73-73) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4_vx.c (+60-60) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4su_vv.c (+75-75) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4su_vx.c (+60-60) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4u_vv.c (+67-67) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4u_vx.c (+60-60) - (modified) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4us_vx.c (+60-60) - (modified) llvm/include/llvm/IR/IntrinsicsRISCV.td (+4-4) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZvdot4a8i.td (+25-39) - (modified) llvm/test/CodeGen/RISCV/rvv/vdota4.ll (+52-52) - (modified) llvm/test/CodeGen/RISCV/rvv/vdota4su.ll (+52-52) - (modified) llvm/test/CodeGen/RISCV/rvv/vdota4u.ll (+52-52) - (modified) llvm/test/CodeGen/RISCV/rvv/vdota4us.ll (+20-20) ``````````diff diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td index 9ddc63bdda75e..6d45e6ca94cd1 100644 --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -2107,7 +2107,7 @@ multiclass RVVVDOTA4QBuiltinSet<list<list<string>> suffixes_prototypes> { HasMaskedOffOperand = false, OverloadedName = NAME, Log2LMUL = [-1, 0, 1, 2, 3] in { - defm NAME : RVVOutOp1Op2BuiltinSet<NAME, "i", suffixes_prototypes>; + defm NAME : RVVOutOp2BuiltinSet<NAME, "i", suffixes_prototypes>; } } @@ -2115,13 +2115,13 @@ multiclass RVVVDOTA4QBuiltinSet<list<list<string>> suffixes_prototypes> { // four 8-bit integer bundles, we use unsigned type to represent all of them let RequiredFeatures = ["zvdot4a8i"] in { defm vdota4 - : RVVVDOTA4QBuiltinSet<[["vv", "v", "vv(FixedSEW:8)v(FixedSEW:8)v"], - ["vx", "v", "vv(FixedSEW:8)vUe"]]>; + : RVVVDOTA4QBuiltinSet<[["vv", "v", "vvUvUv"], + ["vx", "v", "vvUvUe"]]>; defm vdota4u - : RVVVDOTA4QBuiltinSet<[["vv", "Uv", "UvUv(FixedSEW:8)Uv(FixedSEW:8)Uv"], - ["vx", "Uv", "UvUv(FixedSEW:8)UvUe"]]>; + : RVVVDOTA4QBuiltinSet<[["vv", "Uv", "UvUvUvUv"], + ["vx", "Uv", "UvUvUvUe"]]>; defm vdota4su - : RVVVDOTA4QBuiltinSet<[["vv", "v", "vv(FixedSEW:8)v(FixedSEW:8)Uv"], - ["vx", "v", "vv(FixedSEW:8)vUe"]]>; - defm vdota4us : RVVVDOTA4QBuiltinSet<[["vx", "v", "vv(FixedSEW:8)UvUe"]]>; + : RVVVDOTA4QBuiltinSet<[["vv", "v", "vvUvUv"], + ["vx", "v", "vvUvUe"]]>; + defm vdota4us : RVVVDOTA4QBuiltinSet<[["vx", "v", "vvUvUe"]]>; } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vv.c index 90d90c514b1d9..22f9053ce4a18 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vv.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vv.c @@ -7,111 +7,111 @@ #include <sifive_vector.h> // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2( -// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // -vint32mf2_t test_vdota4_vv_i32mf2(vint32mf2_t vd, vint8mf2_t vs2, vint8mf2_t vs1, +vint32mf2_t test_vdota4_vv_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) { return __riscv_vdota4_vv_i32mf2(vd, vs2, vs1, vl); } // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1( -// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // -vint32m1_t test_vdota4_vv_i32m1(vint32m1_t vd, vint8m1_t vs2, vint8m1_t vs1, +vint32m1_t test_vdota4_vv_i32m1(vint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) { return __riscv_vdota4_vv_i32m1(vd, vs2, vs1, vl); } // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2( -// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // -vint32m2_t test_vdota4_vv_i32m2(vint32m2_t vd, vint8m2_t vs2, vint8m2_t vs1, +vint32m2_t test_vdota4_vv_i32m2(vint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) { return __riscv_vdota4_vv_i32m2(vd, vs2, vs1, vl); } // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4( -// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // -vint32m4_t test_vdota4_vv_i32m4(vint32m4_t vd, vint8m4_t vs2, vint8m4_t vs1, +vint32m4_t test_vdota4_vv_i32m4(vint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) { return __riscv_vdota4_vv_i32m4(vd, vs2, vs1, vl); } // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8( -// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // -vint32m8_t test_vdota4_vv_i32m8(vint32m8_t vd, vint8m8_t vs2, vint8m8_t vs1, +vint32m8_t test_vdota4_vv_i32m8(vint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) { return __riscv_vdota4_vv_i32m8(vd, vs2, vs1, vl); } // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2_m( -// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], <vscale x 1 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv1i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], <vscale x 1 x i32> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // -vint32mf2_t test_vdota4_vv_i32mf2_m(vbool64_t vm, vint32mf2_t vd, vint8mf2_t vs2, - vint8mf2_t vs1, size_t vl) { +vint32mf2_t test_vdota4_vv_i32mf2_m(vbool64_t vm, vint32mf2_t vd, vuint32mf2_t vs2, + vuint32mf2_t vs1, size_t vl) { return __riscv_vdota4_vv_i32mf2_m(vm, vd, vs2, vs1, vl); } // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1_m( -// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], <vscale x 2 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], <vscale x 2 x i32> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // -vint32m1_t test_vdota4_vv_i32m1_m(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2, - vint8m1_t vs1, size_t vl) { +vint32m1_t test_vdota4_vv_i32m1_m(vbool32_t vm, vint32m1_t vd, vuint32m1_t vs2, + vuint32m1_t vs1, size_t vl) { return __riscv_vdota4_vv_i32m1_m(vm, vd, vs2, vs1, vl); } // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2_m( -// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], <vscale x 4 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv4i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], <vscale x 4 x i32> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // -vint32m2_t test_vdota4_vv_i32m2_m(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2, - vint8m2_t vs1, size_t vl) { +vint32m2_t test_vdota4_vv_i32m2_m(vbool16_t vm, vint32m2_t vd, vuint32m2_t vs2, + vuint32m2_t vs1, size_t vl) { return __riscv_vdota4_vv_i32m2_m(vm, vd, vs2, vs1, vl); } // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4_m( -// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], <vscale x 8 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv8i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], <vscale x 8 x i32> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // -vint32m4_t test_vdota4_vv_i32m4_m(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2, - vint8m4_t vs1, size_t vl) { +vint32m4_t test_vdota4_vv_i32m4_m(vbool8_t vm, vint32m4_t vd, vuint32m4_t vs2, + vuint32m4_t vs1, size_t vl) { return __riscv_vdota4_vv_i32m4_m(vm, vd, vs2, vs1, vl); } // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8_m( -// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], <vscale x 16 x i32> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv16i32.i64(<vscale x 16 x i32> [[VD]], <vscale x 16 x i32> [[VS2]], <vscale x 16 x i32> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // -vint32m8_t test_vdota4_vv_i32m8_m(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2, - vint8m8_t vs1, size_t vl) { +vint32m8_t test_vdota4_vv_i32m8_m(vbool4_t vm, vint32m8_t vd, vuint32m8_t vs2, + vuint32m8_t vs1, size_t vl) { return __riscv_vdota4_vv_i32m8_m(vm, vd, vs2, vs1, vl); } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vx.c index 42dadc90606a9..2045577d58ca1 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vx.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vx.c @@ -7,111 +7,111 @@ #include <sifive_vector.h> // CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2( -// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 1 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 1 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // -vint32mf2_t test_vdota4_vx_i32mf2(vint32mf2_t vd, vint8mf2_t vs2, uint32_t rs1, +vint32mf2_t test_vdota4_vx_i32mf2(vint32mf2_t vd, vuint32mf2_t vs2, uint32_t rs1, size_t vl) { return __riscv_vdota4_vx_i32mf2(vd, vs2, rs1, vl); } // CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1( -// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 2 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 2 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // -vint32m1_t test_vdota4_vx_i32m1(vint32m1_t vd, vint8m1_t vs2, uint32_t rs1, +vint32m1_t test_vdota4_vx_i32m1(vint32m1_t vd, vuint32m1_t vs2, uint32_t rs1, size_t vl) { return __riscv_vdota4_vx_i32m1(vd, vs2, rs1, vl); } // CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2( -// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 4 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 4 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // -vint32m2_t test_vdota4_vx_i32m2(vint32m2_t vd, vint8m2_t vs2, uint32_t rs1, +vint32m2_t test_vdota4_vx_i32m2(vint32m2_t vd, vuint32m2_t vs2, uint32_t rs1, size_t vl) { return __riscv_vdota4_vx_i32m2(vd, vs2, rs1, vl); } // CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vx_i32m4( -// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 8 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.nxv32i8.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.i32.i64(<vscale x 8 x i32> [[VD]], <vscale x 8 x i32> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // -vint32m4_t test_vdota4_vx_i32m4(vint32m4_t vd, vint8m4_t vs2, uint32_t rs1, +vint32m4_t test_vdota4_vx_i32m4(vint32m4_t vd, vuint32m4_t vs2, uint32_t rs1, size_t vl) { return __riscv_vdota4_vx_i32m4(vd, vs2, rs1, vl); } // CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vx_i32m8( -// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 16 x i32> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.r... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/184089 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
