================
@@ -6356,6 +6356,79 @@ SDValue
AArch64TargetLowering::LowerINTRINSIC_VOID(SDValue Op,
Op.getOperand(0), // Chain
DAG.getTargetConstant(24, DL, MVT::i32), // Rt
Op.getOperand(2)); // Addr
+ case Intrinsic::aarch64_stshh_atomic_store: {
+ SDValue Chain = Op.getOperand(0);
+ SDValue Ptr = Op.getOperand(2);
+ SDValue Val = Op.getOperand(3);
+ auto *OrderC = cast<ConstantSDNode>(Op.getOperand(4));
+ auto *PolicyC = cast<ConstantSDNode>(Op.getOperand(5));
+ uint64_t OrderVal = OrderC->getZExtValue();
+
+ unsigned SizeBits = Val.getValueType().getSizeInBits();
+ if (SizeBits < 8)
+ SizeBits = 8;
+ unsigned PseudoOpc = 0;
+ // Select pseudo opcode based on value size.
+ switch (SizeBits) {
+ case 8:
+ PseudoOpc = AArch64::STSHH_ATOMIC_STORE_B;
+ break;
+ case 16:
+ PseudoOpc = AArch64::STSHH_ATOMIC_STORE_H;
+ break;
+ case 32:
+ PseudoOpc = AArch64::STSHH_ATOMIC_STORE_W;
+ break;
+ case 64:
+ PseudoOpc = AArch64::STSHH_ATOMIC_STORE_X;
+ break;
+ default:
+ llvm_unreachable("Unexpected STSHH atomic store size");
+ }
+
+ // Extend or truncate value to expected store width
+ if (SizeBits <= 32)
+ Val = DAG.getAnyExtOrTrunc(Val, DL, MVT::i32);
+ else
+ Val = DAG.getAnyExtOrTrunc(Val, DL, MVT::i64);
+
+ SDValue Order = DAG.getTargetConstant(OrderVal, DL, MVT::i32);
+ SDValue Policy =
+ DAG.getTargetConstant(PolicyC->getZExtValue(), DL, MVT::i32);
+
+ // Build pseudo which expands to STSHH + atomic store.
+ SDValue Ops[] = {Val, Ptr, Order, Policy, Chain};
+ MachineSDNode *N = DAG.getMachineNode(PseudoOpc, DL, MVT::Other, Ops);
----------------
jthackray wrote:
Thanks. I've moved code to `getTgtMemIntrinsic` and added a tablegen pattern to
match this intrinsic.
https://github.com/llvm/llvm-project/pull/181386
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