Author: Andrzej Warzyński Date: 2026-02-23T10:17:56Z New Revision: f8906704104e446a7482aeca32d058b91867e05c
URL: https://github.com/llvm/llvm-project/commit/f8906704104e446a7482aeca32d058b91867e05c DIFF: https://github.com/llvm/llvm-project/commit/f8906704104e446a7482aeca32d058b91867e05c.diff LOG: [CIR][ARM] Refactor argument handling in `emitAArch64BuiltinExpr` (NFC) (#182105) Port recent argument-handling refactors from CodeGen/TargetBuiltins/ARM.cpp into CIR/CodeGen/CIRGenBuiltinAArch64.cpp to keep the CIR implementation in sync with Clang CodeGen. In particular, mirror the updated handling of Sema-only NEON discriminator arguments and the common argument emission logic used to populate the `Ops` vector. This is a mechanical port of the following changes: * https://github.com/llvm/llvm-project/pull/181974 * https://github.com/llvm/llvm-project/pull/181794 No functional change intended. Added: Modified: clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp Removed: ################################################################################ diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index 699fee5a3a358..16fe3142f2bc6 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -240,6 +240,40 @@ static unsigned getSVEMinEltCount(clang::SVETypeFlags::EltType sveType) { } } +/// Return true if BuiltinID is an overloaded Neon intrinsic with an extra +/// argument that specifies the vector type. The additional argument is meant +/// for Sema checking (see `CheckNeonBuiltinFunctionCall`) and this function +/// should be kept consistent with the logic in Sema. +/// TODO: Make this return false for SISD builtins. +/// TODO: Share this with ARM.cpp +static bool hasExtraNeonArgument(unsigned builtinID) { + // Required by the headers included below, but not in this particular + // function. + [[maybe_unused]] int PtrArgNum = -1; + [[maybe_unused]] bool HasConstPtr = false; + + // The mask encodes the type. We don't care about the actual value. Instead, + // we just check whether its been set. + uint64_t mask = 0; + switch (builtinID) { +#define GET_NEON_OVERLOAD_CHECK +#include "clang/Basic/arm_fp16.inc" +#include "clang/Basic/arm_neon.inc" +#undef GET_NEON_OVERLOAD_CHECK + // Non-neon builtins for controling VFP that take extra argument for + // discriminating the type. + case ARM::BI__builtin_arm_vcvtr_f: + case ARM::BI__builtin_arm_vcvtr_d: + mask = 1; + } + switch (builtinID) { + default: + break; + } + + return mask != 0; +} + std::optional<mlir::Value> CIRGenFunction::emitAArch64SVEBuiltinExpr(unsigned builtinID, const CallExpr *expr) { @@ -1360,8 +1394,13 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, getContext().GetBuiltinType(builtinID, error, &iceArguments); assert(error == ASTContext::GE_None && "Should not codegen an error"); llvm::SmallVector<mlir::Value> ops; - for (auto [idx, arg] : llvm::enumerate(expr->arguments())) { - if (idx == 0) { + + // Skip extra arguments used to discriminate vector types and that are + // intended for Sema checking. + bool hasExtraArg = hasExtraNeonArgument(builtinID); + unsigned numArgs = expr->getNumArgs() - (hasExtraArg ? 1 : 0); + for (unsigned i = 0, e = numArgs; i != e; i++) { + if (i == 0) { switch (builtinID) { case NEON::BI__builtin_neon_vld1_v: case NEON::BI__builtin_neon_vld1q_v: @@ -1385,11 +1424,18 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, getContext().BuiltinInfo.getName(builtinID)); } } - ops.push_back(emitScalarOrConstFoldImmArg(iceArguments, idx, arg)); + ops.push_back( + emitScalarOrConstFoldImmArg(iceArguments, i, expr->getArg(i))); } assert(!cir::MissingFeatures::neonSISDIntrinsics()); + // Not all intrinsics handled by the common case work for AArch64 yet, so only + // defer to common code if it's been added to our special map. + assert(!cir::MissingFeatures::aarch64SIMDIntrinsics()); + + assert(!cir::MissingFeatures::aarch64TblBuiltinExpr()); + mlir::Location loc = getLoc(expr->getExprLoc()); // Handle non-overloaded intrinsics first. @@ -1614,12 +1660,6 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, return mlir::Value{}; } - // Not all intrinsics handled by the common case work for AArch64 yet, so only - // defer to common code if it's been added to our special map. - assert(!cir::MissingFeatures::aarch64SIMDIntrinsics()); - - assert(!cir::MissingFeatures::aarch64TblBuiltinExpr()); - switch (builtinID) { default: return std::nullopt; _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
