https://github.com/KungFuDonkey updated https://github.com/llvm/llvm-project/pull/165156
>From 04af5789d6323d2b4bc128909da1e9450ff2e374 Mon Sep 17 00:00:00 2001 From: KungFuDonkey <[email protected]> Date: Sun, 26 Oct 2025 15:13:11 +0100 Subject: [PATCH 01/13] Added WaveActiveBitOr --- clang/include/clang/Basic/Builtins.td | 6 +++ clang/lib/CodeGen/CGHLSLBuiltins.cpp | 9 +++++ clang/lib/CodeGen/CGHLSLRuntime.h | 1 + .../lib/Headers/hlsl/hlsl_alias_intrinsics.h | 30 +++++++++++++++ clang/lib/Sema/SemaHLSL.cpp | 23 +++++++++++ .../CodeGenHLSL/builtins/WaveActiveBitOr.hlsl | 30 +++++++++++++++ .../BuiltIns/WaveActiveBitOr-errors.hlsl | 38 +++++++++++++++++++ llvm/include/llvm/IR/IntrinsicsDirectX.td | 1 + llvm/include/llvm/IR/IntrinsicsSPIRV.td | 3 +- llvm/lib/Target/DirectX/DXIL.td | 22 +++++++++++ llvm/lib/Target/DirectX/DXILShaderFlags.cpp | 1 + .../DirectX/DirectXTargetTransformInfo.cpp | 1 + .../Target/SPIRV/SPIRVInstructionSelector.cpp | 31 +++++++++++++++ .../CodeGen/DirectX/ShaderFlags/wave-ops.ll | 7 ++++ llvm/test/CodeGen/DirectX/WaveActiveBitOr.ll | 19 ++++++++++ .../SPIRV/hlsl-intrinsics/WaveActiveBitOr.ll | 30 +++++++++++++++ 16 files changed, 251 insertions(+), 1 deletion(-) create mode 100644 clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl create mode 100644 clang/test/SemaHLSL/BuiltIns/WaveActiveBitOr-errors.hlsl create mode 100644 llvm/test/CodeGen/DirectX/WaveActiveBitOr.ll create mode 100644 llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveBitOr.ll diff --git a/clang/include/clang/Basic/Builtins.td b/clang/include/clang/Basic/Builtins.td index 792e2e07ec594..3eff68e5b7b8f 100644 --- a/clang/include/clang/Basic/Builtins.td +++ b/clang/include/clang/Basic/Builtins.td @@ -4999,6 +4999,12 @@ def HLSLWaveActiveAnyTrue : LangBuiltin<"HLSL_LANG"> { let Prototype = "bool(bool)"; } +def HLSLWaveActiveBitOr : LangBuiltin<"HLSL_LANG"> { + let Spellings = ["__builtin_hlsl_wave_active_bit_or"]; + let Attributes = [NoThrow, Const]; + let Prototype = "void (...)"; +} + def HLSLWaveActiveCountBits : LangBuiltin<"HLSL_LANG"> { let Spellings = ["__builtin_hlsl_wave_active_count_bits"]; let Attributes = [NoThrow, Const]; diff --git a/clang/lib/CodeGen/CGHLSLBuiltins.cpp b/clang/lib/CodeGen/CGHLSLBuiltins.cpp index 4f2f5a761f197..2668f223aaa8f 100644 --- a/clang/lib/CodeGen/CGHLSLBuiltins.cpp +++ b/clang/lib/CodeGen/CGHLSLBuiltins.cpp @@ -690,6 +690,15 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, return EmitRuntimeCall( Intrinsic::getOrInsertDeclaration(&CGM.getModule(), ID), {Op}); } + case Builtin::BI__builtin_hlsl_wave_active_bit_or: { + Value *Op = EmitScalarExpr(E->getArg(0)); + assert(Op->getType()->hasUnsignedIntegerRepresentation() && + "Intrinsic WaveActiveBitOr operand must have a unsigned integer representation"); + + Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveActiveBitOrIntrinsic(); + return EmitRuntimeCall( + Intrinsic::getOrInsertDeclaration(&CGM.getModule(), ID), {Op}); + } case Builtin::BI__builtin_hlsl_wave_active_count_bits: { Value *OpExpr = EmitScalarExpr(E->getArg(0)); Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveActiveCountBitsIntrinsic(); diff --git a/clang/lib/CodeGen/CGHLSLRuntime.h b/clang/lib/CodeGen/CGHLSLRuntime.h index 7c6c2850fd4d4..b7fb15f10b6c5 100644 --- a/clang/lib/CodeGen/CGHLSLRuntime.h +++ b/clang/lib/CodeGen/CGHLSLRuntime.h @@ -113,6 +113,7 @@ class CGHLSLRuntime { GENERATE_HLSL_INTRINSIC_FUNCTION(Dot4AddU8Packed, dot4add_u8packed) GENERATE_HLSL_INTRINSIC_FUNCTION(WaveActiveAllTrue, wave_all) GENERATE_HLSL_INTRINSIC_FUNCTION(WaveActiveAnyTrue, wave_any) + GENERATE_HLSL_INTRINSIC_FUNCTION(WaveActiveBitOr, wave_reduce_or) GENERATE_HLSL_INTRINSIC_FUNCTION(WaveActiveCountBits, wave_active_countbits) GENERATE_HLSL_INTRINSIC_FUNCTION(WaveIsFirstLane, wave_is_first_lane) GENERATE_HLSL_INTRINSIC_FUNCTION(WaveGetLaneCount, wave_get_lane_count) diff --git a/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h b/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h index d973371312701..2075f557a9a0a 100644 --- a/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h +++ b/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h @@ -2498,6 +2498,36 @@ __attribute__((convergent)) double3 WaveReadLaneAt(double3, uint32_t); _HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_read_lane_at) __attribute__((convergent)) double4 WaveReadLaneAt(double4, uint32_t); +//===----------------------------------------------------------------------===// +// WaveActiveBitOr builtins +//===----------------------------------------------------------------------===// + +_HLSL_AVAILABILITY(shadermodel, 6.0) +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_bit_or) +__attribute__((convergent)) uint WaveActiveBitOr(uint); +_HLSL_AVAILABILITY(shadermodel, 6.0) +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_bit_or) +__attribute__((convergent)) uint2 WaveActiveBitOr(uint2); +_HLSL_AVAILABILITY(shadermodel, 6.0) +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_bit_or) +__attribute__((convergent)) uint3 WaveActiveBitOr(uint3); +_HLSL_AVAILABILITY(shadermodel, 6.0) +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_bit_or) +__attribute__((convergent)) uint4 WaveActiveBitOr(uint4); + +_HLSL_AVAILABILITY(shadermodel, 6.0) +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_bit_or) +__attribute__((convergent)) uint64_t WaveActiveBitOr(uint64_t); +_HLSL_AVAILABILITY(shadermodel, 6.0) +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_bit_or) +__attribute__((convergent)) uint64_t2 WaveActiveBitOr(uint64_t2); +_HLSL_AVAILABILITY(shadermodel, 6.0) +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_bit_or) +__attribute__((convergent)) uint64_t3 WaveActiveBitOr(uint64_t3); +_HLSL_AVAILABILITY(shadermodel, 6.0) +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_bit_or) +__attribute__((convergent)) uint64_t4 WaveActiveBitOr(uint64_t4); + //===----------------------------------------------------------------------===// // WaveActiveMax builtins //===----------------------------------------------------------------------===// diff --git a/clang/lib/Sema/SemaHLSL.cpp b/clang/lib/Sema/SemaHLSL.cpp index f34706677b59f..5969173b15fab 100644 --- a/clang/lib/Sema/SemaHLSL.cpp +++ b/clang/lib/Sema/SemaHLSL.cpp @@ -3211,6 +3211,29 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { TheCall->setType(ArgTyExpr); break; } + case Builtin::BI__builtin_hlsl_wave_active_bit_or: { + if (SemaRef.checkArgCount(TheCall, 1)) + return true; + + // Ensure input expr type is a scalar/vector and the same as the return type + if (CheckAnyScalarOrVector(&SemaRef, TheCall, 0)) + return true; + if (CheckWaveActive(&SemaRef, TheCall)) + return true; + + // Ensure expression parameter type can be interpreted as a uint + ExprResult Expr = TheCall->getArg(0); + QualType ArgTyExpr = Expr.get()->getType(); + if (!ArgTyExpr->isIntegerType()) { + SemaRef.Diag(TheCall->getArg(0)->getBeginLoc(), + diag::err_typecheck_convert_incompatible) + << ArgTyExpr << SemaRef.Context.UnsignedIntTy << 1 << 0 << 0; + return true; + } + + TheCall->setType(ArgTyExpr); + break; + } // Note these are llvm builtins that we want to catch invalid intrinsic // generation. Normal handling of these builitns will occur elsewhere. case Builtin::BI__builtin_elementwise_bitreverse: { diff --git a/clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl b/clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl new file mode 100644 index 0000000000000..5e030208679b9 --- /dev/null +++ b/clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl @@ -0,0 +1,30 @@ +// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -triple \ +// RUN: dxil-pc-shadermodel6.3-compute %s -emit-llvm -disable-llvm-passes -o - | \ +// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-DXIL +// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -triple \ +// RUN: spirv-pc-vulkan-compute %s -emit-llvm -disable-llvm-passes -o - | \ +// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-SPIRV + +// Test basic lowering to runtime function call. + +// CHECK-LABEL: test_uint +uint test_uint(uint expr) { + // CHECK-SPIRV: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.spv.wave.reduce.or.i32([[TY]] %[[#]]) + // CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.reduce.or.i32([[TY]] %[[#]]) + // CHECK: ret [[TY]] %[[RET]] + return WaveActiveBitOr(expr); +} + +// CHECK-DXIL: declare [[TY]] @llvm.dx.wave.reduce.or.i32([[TY]]) #[[#attr:]] +// CHECK-SPIRV: declare [[TY]] @llvm.spv.wave.reduce.or.i32([[TY]]) #[[#attr:]] + +// CHECK-LABEL: test_uint64_t +uint64_t test_uint64_t(uint64_t expr) { + // CHECK-SPIRV: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.spv.wave.reduce.or.i64([[TY]] %[[#]]) + // CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.reduce.or.i64([[TY]] %[[#]]) + // CHECK: ret [[TY]] %[[RET]] + return WaveActiveBitOr(expr); +} + +// CHECK-DXIL: declare [[TY]] @llvm.dx.wave.reduce.or.i64([[TY]]) #[[#attr:]] +// CHECK-SPIRV: declare [[TY]] @llvm.spv.wave.reduce.or.i64([[TY]]) #[[#attr:]] diff --git a/clang/test/SemaHLSL/BuiltIns/WaveActiveBitOr-errors.hlsl b/clang/test/SemaHLSL/BuiltIns/WaveActiveBitOr-errors.hlsl new file mode 100644 index 0000000000000..8eb62c7d96b4e --- /dev/null +++ b/clang/test/SemaHLSL/BuiltIns/WaveActiveBitOr-errors.hlsl @@ -0,0 +1,38 @@ +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -emit-llvm-only -disable-llvm-passes -verify + +uint test_too_few_arg() { + return __builtin_hlsl_wave_active_bit_or(); + // expected-error@-1 {{too few arguments to function call, expected 1, have 0}} +} + +uint2 test_too_many_arg(uint2 p0) { + return __builtin_hlsl_wave_active_bit_or(p0, p0); + // expected-error@-1 {{too many arguments to function call, expected 1, have 2}} +} + +bool test_expr_bool_type_check(bool p0) { + return __builtin_hlsl_wave_active_bit_or(p0); + // expected-error@-1 {{invalid operand of type 'bool'}} +} + +float test_expr_float_type_check(float p0) { + return __builtin_hlsl_wave_active_bit_or(p0); + // expected-error@-1 {{invalid operand of type 'float'}} +} + +bool2 test_expr_bool_vec_type_check(bool2 p0) { + return __builtin_hlsl_wave_active_bit_or(p0); + // expected-error@-1 {{invalid operand of type 'bool2' (aka 'vector<bool, 2>')}} +} + +float2 test_expr_float_type_check(float2 p0) { + return __builtin_hlsl_wave_active_bit_or(p0); + // expected-error@-1 {{invalid operand of type 'float2' (aka 'vector<float, 2>')}} +} + +struct S { float f; }; + +S test_expr_struct_type_check(S p0) { + return __builtin_hlsl_wave_active_bit_or(p0); + // expected-error@-1 {{invalid operand of type 'S' where a scalar or vector is required}} +} diff --git a/llvm/include/llvm/IR/IntrinsicsDirectX.td b/llvm/include/llvm/IR/IntrinsicsDirectX.td index 3b7077c52db21..22f5644c1103e 100644 --- a/llvm/include/llvm/IR/IntrinsicsDirectX.td +++ b/llvm/include/llvm/IR/IntrinsicsDirectX.td @@ -151,6 +151,7 @@ def int_dx_wave_active_countbits : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i1 def int_dx_wave_all : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>; def int_dx_wave_any : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>; def int_dx_wave_getlaneindex : DefaultAttrsIntrinsic<[llvm_i32_ty], [], [IntrConvergent, IntrNoMem]>; +def int_dx_wave_reduce_or : DefaultAttrsIntrinsic<[llvm_anyint_ty], [llvm_anyint_ty], [IntrConvergent, IntrNoMem]>; def int_dx_wave_reduce_max : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; def int_dx_wave_reduce_umax : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; def int_dx_wave_reduce_sum : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td index 49a182be98acd..8747c46c97293 100644 --- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td +++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td @@ -120,6 +120,7 @@ def int_spv_rsqrt : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty] def int_spv_wave_active_countbits : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>; def int_spv_wave_all : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>; def int_spv_wave_any : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>; + def int_spv_wave_reduce_or : DefaultAttrsIntrinsic<[llvm_anyint_ty], [llvm_anyint_ty], [IntrConvergent, IntrNoMem]>; def int_spv_wave_reduce_umax : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; def int_spv_wave_reduce_max : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; def int_spv_wave_reduce_sum : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; @@ -136,7 +137,7 @@ def int_spv_rsqrt : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty] def int_spv_sclamp : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; def int_spv_nclamp : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; - // Create resource handle given the binding information. Returns a + // Create resource handle given the binding information. Returns a // type appropriate for the kind of resource given the set id, binding id, // array size of the binding, as well as an index and an indicator // whether that index may be non-uniform. diff --git a/llvm/lib/Target/DirectX/DXIL.td b/llvm/lib/Target/DirectX/DXIL.td index 44c48305f2832..537eba6afd0a2 100644 --- a/llvm/lib/Target/DirectX/DXIL.td +++ b/llvm/lib/Target/DirectX/DXIL.td @@ -316,6 +316,10 @@ defvar WaveOpKind_Product = 1; defvar WaveOpKind_Min = 2; defvar WaveOpKind_Max = 3; +defvar WaveBitOpKind_And = 0; +defvar WaveBitOpKind_Or = 1; +defvar WaveBitOpKind_Xor = 2; + defvar SignedOpKind_Signed = 0; defvar SignedOpKind_Unsigned = 1; @@ -1069,6 +1073,24 @@ def WaveActiveOp : DXILOp<119, waveActiveOp> { let attributes = [Attributes<DXIL1_0, []>]; } +def WaveActiveBit : DXILOp<120, waveActiveBit> { + let Doc = "returns the result of the operation across waves"; + let intrinsics = [ + IntrinSelect<int_dx_wave_reduce_or, + [ + IntrinArgIndex<0>, IntrinArgI8<WaveBitOpKind_Or>, + ]>, + ]; + + let arguments = [OverloadTy, Int8Ty]; + let result = OverloadTy; + let overloads = [ + Overloads<DXIL1_0, [Int32Ty, Int64Ty]> + ]; + let stages = [Stages<DXIL1_0, [all_stages]>]; + let attributes = [Attributes<DXIL1_0, []>]; +} + def WaveAllBitCount : DXILOp<135, waveAllOp> { let Doc = "returns the count of bits set to 1 across the wave"; let intrinsics = [IntrinSelect<int_dx_wave_active_countbits>]; diff --git a/llvm/lib/Target/DirectX/DXILShaderFlags.cpp b/llvm/lib/Target/DirectX/DXILShaderFlags.cpp index e7e7f2ce66ae8..7c47e107f51b3 100644 --- a/llvm/lib/Target/DirectX/DXILShaderFlags.cpp +++ b/llvm/lib/Target/DirectX/DXILShaderFlags.cpp @@ -90,6 +90,7 @@ static bool checkWaveOps(Intrinsic::ID IID) { case Intrinsic::dx_wave_readlane: case Intrinsic::dx_wave_active_countbits: // Wave Active Op Variants + case Intrinsic::dx_wave_reduce_or: case Intrinsic::dx_wave_reduce_sum: case Intrinsic::dx_wave_reduce_usum: case Intrinsic::dx_wave_reduce_max: diff --git a/llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp b/llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp index 68fd3e0bc74c7..50b7e9fd957f5 100644 --- a/llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp +++ b/llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp @@ -54,6 +54,7 @@ bool DirectXTTIImpl::isTargetIntrinsicTriviallyScalarizable( case Intrinsic::dx_saturate: case Intrinsic::dx_splitdouble: case Intrinsic::dx_wave_readlane: + case Intrinsic::dx_wave_reduce_or: case Intrinsic::dx_wave_reduce_max: case Intrinsic::dx_wave_reduce_sum: case Intrinsic::dx_wave_reduce_umax: diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp index a0cff4d82b500..3429e98de0548 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp @@ -219,6 +219,9 @@ class SPIRVInstructionSelector : public InstructionSelector { bool selectDot4AddPackedExpansion(Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const; + bool selectWaveReduceOr(Register ResVReg, const SPIRVType *ResType, + MachineInstr &I) const; + bool selectWaveReduceMax(Register ResVReg, const SPIRVType *ResType, MachineInstr &I, bool IsUnsigned) const; @@ -2427,6 +2430,32 @@ bool SPIRVInstructionSelector::selectWaveActiveCountBits( return Result; } +bool SPIRVInstructionSelector::selectWaveReduceOr( + Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const { + + assert(I.getNumOperands() == 3); + assert(I.getOperand(2).isReg()); + MachineBasicBlock &BB = *I.getParent(); + Register InputRegister = I.getOperand(2).getReg(); + SPIRVType *InputType = GR.getSPIRVTypeForVReg(InputRegister); + + if (!InputType) + report_fatal_error("Input Type could not be determined."); + + SPIRVType *IntTy = GR.getOrCreateSPIRVIntegerType(32, I, TII); + + auto Opcode = SPIRV::OpGroupNonUniformBitwiseOr; + + return BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) + .addDef(ResVReg) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(GR.getOrCreateConstInt(SPIRV::Scope::Subgroup, I, IntTy, TII, + !STI.isShader())) + .addImm(SPIRV::GroupOperation::Reduce) + .addUse(I.getOperand(2).getReg()) + .constrainAllUses(TII, TRI, RBI); +} + bool SPIRVInstructionSelector::selectWaveReduceMax(Register ResVReg, const SPIRVType *ResType, MachineInstr &I, @@ -3427,6 +3456,8 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformAny); case Intrinsic::spv_wave_is_first_lane: return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformElect); + case Intrinsic::spv_wave_reduce_or: + return selectWaveReduceOr(ResVReg, ResType, I); case Intrinsic::spv_wave_reduce_umax: return selectWaveReduceMax(ResVReg, ResType, I, /*IsUnsigned*/ true); case Intrinsic::spv_wave_reduce_max: diff --git a/llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll b/llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll index 7a876f67615cd..140152aa80c07 100644 --- a/llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll +++ b/llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll @@ -41,6 +41,13 @@ entry: ret i1 %ret } +define noundef i32 @wave_bit_or(i32 %x) { +entry: + ; CHECK: Function wave_bit_or : [[WAVE_FLAG]] + %ret = call i32 @llvm.dx.wave.reduce.or(i32 %x) + ret i32 %ret +} + define noundef i1 @wave_readlane(i1 %x, i32 %idx) { entry: ; CHECK: Function wave_readlane : [[WAVE_FLAG]] diff --git a/llvm/test/CodeGen/DirectX/WaveActiveBitOr.ll b/llvm/test/CodeGen/DirectX/WaveActiveBitOr.ll new file mode 100644 index 0000000000000..386a263ec245d --- /dev/null +++ b/llvm/test/CodeGen/DirectX/WaveActiveBitOr.ll @@ -0,0 +1,19 @@ +; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-compute %s | FileCheck %s + +define noundef i32 @wave_bitor_simple(i32 noundef %p1) { +entry: +; CHECK: call i32 @dx.op.waveActiveBit.i32(i32 120, i32 %p1, i8 1){{$}} + %ret = call i32 @llvm.dx.wave.reduce.or.i32(i32 %p1) + ret i32 %ret +} + +declare i32 @llvm.dx.wave.reduce.or.i32(i32) + +define noundef i64 @wave_bitor_simple64(i64 noundef %p1) { +entry: +; CHECK: call i64 @dx.op.waveActiveBit.i64(i32 120, i64 %p1, i8 1){{$}} + %ret = call i64 @llvm.dx.wave.reduce.or.i64(i64 %p1) + ret i64 %ret +} + +declare i64 @llvm.dx.wave.reduce.or.i64(i64) diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveBitOr.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveBitOr.ll new file mode 100644 index 0000000000000..2df3a335bee69 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveBitOr.ll @@ -0,0 +1,30 @@ +; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %} + +; Test lowering to spir-v backend for various types and scalar/vector + +; CHECK-DAG: %[[#uint:]] = OpTypeInt 32 0 +; CHECK-DAG: %[[#uint64:]] = OpTypeInt 64 0 +; CHECK-DAG: %[[#scope:]] = OpConstant %[[#uint]] 3 + +; CHECK-LABEL: Begin function test_uint +; CHECK: %[[#iexpr:]] = OpFunctionParameter %[[#uint]] +define i32 @test_uint(i32 %iexpr) { +entry: +; CHECK: %[[#iret:]] = OpGroupNonUniformBitwiseOr %[[#uint]] %[[#scope]] Reduce %[[#iexpr]] + %0 = call i32 @llvm.spv.wave.reduce.or.i32(i32 %iexpr) + ret i32 %0 +} + +declare i32 @llvm.spv.wave.reduce.or.i32(i32) + +; CHECK-LABEL: Begin function test_uint64 +; CHECK: %[[#iexpr64:]] = OpFunctionParameter %[[#uint64]] +define i64 @test_uint64(i64 %iexpr64) { +entry: +; CHECK: %[[#iret:]] = OpGroupNonUniformBitwiseOr %[[#uint64]] %[[#scope]] Reduce %[[#iexpr64]] + %0 = call i64 @llvm.spv.wave.reduce.or.i64(i64 %iexpr64) + ret i64 %0 +} + +declare i64 @llvm.spv.wave.reduce.or.i64(i64) \ No newline at end of file >From 744fd508e122b8e93b60bddd2ae0292370eba756 Mon Sep 17 00:00:00 2001 From: KungFuDonkey <[email protected]> Date: Wed, 29 Oct 2025 22:42:07 +0100 Subject: [PATCH 02/13] Updated according to review --- clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h | 3 +++ clang/lib/Sema/SemaHLSL.cpp | 12 ++++++------ llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp | 3 +-- .../CodeGen/SPIRV/hlsl-intrinsics/WaveActiveBitOr.ll | 4 ++-- 4 files changed, 12 insertions(+), 10 deletions(-) diff --git a/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h b/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h index 2075f557a9a0a..2f26b36c963b8 100644 --- a/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h +++ b/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h @@ -2502,6 +2502,9 @@ __attribute__((convergent)) double4 WaveReadLaneAt(double4, uint32_t); // WaveActiveBitOr builtins //===----------------------------------------------------------------------===// +// \brief Returns the value of the expression for the given lane index within +// the specified wave. + _HLSL_AVAILABILITY(shadermodel, 6.0) _HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_bit_or) __attribute__((convergent)) uint WaveActiveBitOr(uint); diff --git a/clang/lib/Sema/SemaHLSL.cpp b/clang/lib/Sema/SemaHLSL.cpp index 5969173b15fab..7c6fa14ade639 100644 --- a/clang/lib/Sema/SemaHLSL.cpp +++ b/clang/lib/Sema/SemaHLSL.cpp @@ -3215,22 +3215,22 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { if (SemaRef.checkArgCount(TheCall, 1)) return true; - // Ensure input expr type is a scalar/vector and the same as the return type - if (CheckAnyScalarOrVector(&SemaRef, TheCall, 0)) - return true; if (CheckWaveActive(&SemaRef, TheCall)) return true; - // Ensure expression parameter type can be interpreted as a uint + // Ensure the expr type is interpretable as a uint or vector<uint> ExprResult Expr = TheCall->getArg(0); QualType ArgTyExpr = Expr.get()->getType(); - if (!ArgTyExpr->isIntegerType()) { + auto *VTy = ArgTyExpr->getAs<VectorType>(); + if (!(ArgTyExpr->isIntegerType() || + (VTy && VTy->getElementType()->isIntegerType()))) { SemaRef.Diag(TheCall->getArg(0)->getBeginLoc(), - diag::err_typecheck_convert_incompatible) + diag::err_builtin_invalid_arg_type) << ArgTyExpr << SemaRef.Context.UnsignedIntTy << 1 << 0 << 0; return true; } + // Ensure input expr type is the same as the return type TheCall->setType(ArgTyExpr); break; } diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp index 3429e98de0548..088d684921d70 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp @@ -2015,8 +2015,7 @@ bool SPIRVInstructionSelector::selectAnyOrAll(Register ResVReg, Register InputRegister = I.getOperand(2).getReg(); SPIRVType *InputType = GR.getSPIRVTypeForVReg(InputRegister); - if (!InputType) - report_fatal_error("Input Type could not be determined."); + assert(InputType && "VReg has no type assigned"); bool IsBoolTy = GR.isScalarOrVectorOfType(InputRegister, SPIRV::OpTypeBool); bool IsVectorTy = InputType->getOpcode() == SPIRV::OpTypeVector; diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveBitOr.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveBitOr.ll index 2df3a335bee69..76212dfe86a39 100644 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveBitOr.ll +++ b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveBitOr.ll @@ -1,5 +1,5 @@ ; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %} +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan %s -o - -filetype=obj | spirv-val --target-env spv1.4 %} ; Test lowering to spir-v backend for various types and scalar/vector @@ -27,4 +27,4 @@ entry: ret i64 %0 } -declare i64 @llvm.spv.wave.reduce.or.i64(i64) \ No newline at end of file +declare i64 @llvm.spv.wave.reduce.or.i64(i64) >From 09e85ea4554f7c82118871782154a71b391989a3 Mon Sep 17 00:00:00 2001 From: KungFuDonkey <[email protected]> Date: Sun, 2 Nov 2025 12:27:51 +0100 Subject: [PATCH 03/13] DX and SPV checks --- .../CodeGenHLSL/builtins/WaveActiveBitOr.hlsl | 21 ++++++++++--------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl b/clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl index 5e030208679b9..cfb3d2514cdde 100644 --- a/clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl +++ b/clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl @@ -1,30 +1,31 @@ // RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -triple \ // RUN: dxil-pc-shadermodel6.3-compute %s -emit-llvm -disable-llvm-passes -o - | \ -// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-DXIL +// RUN: FileCheck %s --check-prefixes=CHECK,DXCHECK + // RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -triple \ // RUN: spirv-pc-vulkan-compute %s -emit-llvm -disable-llvm-passes -o - | \ -// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-SPIRV +// RUN: FileCheck %s --check-prefixes=CHECK,SPVCHECK + +// DXCHECK: define hidden [[FN_TYPE:]]noundef i1 @ +// SPVCHECK: define hidden [[FN_TYPE:spir_func ]]noundef i1 @ // Test basic lowering to runtime function call. // CHECK-LABEL: test_uint uint test_uint(uint expr) { - // CHECK-SPIRV: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.spv.wave.reduce.or.i32([[TY]] %[[#]]) - // CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.reduce.or.i32([[TY]] %[[#]]) + // DXCHECK: %[[RET:.*]] = call i1 [[TY:.*]] @llvm.[[ICF:dx]].wave.reduce.or.i32([[TY]] %[[#]]) + // SPVCHECK: %[[RET:.*]] = call i1 [[TY:.*]] @llvm.[[ICF:spv]].wave.reduce.or.i32([[TY]] %[[#]]) // CHECK: ret [[TY]] %[[RET]] return WaveActiveBitOr(expr); } -// CHECK-DXIL: declare [[TY]] @llvm.dx.wave.reduce.or.i32([[TY]]) #[[#attr:]] -// CHECK-SPIRV: declare [[TY]] @llvm.spv.wave.reduce.or.i32([[TY]]) #[[#attr:]] +// CHECK: declare [[TY]] @llvm.[[ICF]].wave.reduce.or.i32([[TY]]) #[[#attr:]] // CHECK-LABEL: test_uint64_t uint64_t test_uint64_t(uint64_t expr) { - // CHECK-SPIRV: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.spv.wave.reduce.or.i64([[TY]] %[[#]]) - // CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.reduce.or.i64([[TY]] %[[#]]) + // CHECK: %[[RET:.*]] = call i1 [[TY:.*]] @llvm.[[ICF]].wave.reduce.or.i64([[TY]] %[[#]]) // CHECK: ret [[TY]] %[[RET]] return WaveActiveBitOr(expr); } -// CHECK-DXIL: declare [[TY]] @llvm.dx.wave.reduce.or.i64([[TY]]) #[[#attr:]] -// CHECK-SPIRV: declare [[TY]] @llvm.spv.wave.reduce.or.i64([[TY]]) #[[#attr:]] +// CHECK: declare [[TY]] @llvm.[[ICF]].wave.reduce.or.i64([[TY]]) #[[#attr:]] >From a8c179af9d0124c08cfb18321e639422338cd446 Mon Sep 17 00:00:00 2001 From: KungFuDonkey <[email protected]> Date: Sun, 2 Nov 2025 13:00:48 +0100 Subject: [PATCH 04/13] Scalarized check --- llvm/test/CodeGen/DirectX/WaveActiveBitOr.ll | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/test/CodeGen/DirectX/WaveActiveBitOr.ll b/llvm/test/CodeGen/DirectX/WaveActiveBitOr.ll index 386a263ec245d..0ee7739cf47d0 100644 --- a/llvm/test/CodeGen/DirectX/WaveActiveBitOr.ll +++ b/llvm/test/CodeGen/DirectX/WaveActiveBitOr.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-compute %s | FileCheck %s +; RUN: opt -S -scalarizer -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-compute %s | FileCheck %s define noundef i32 @wave_bitor_simple(i32 noundef %p1) { entry: >From 1fe4ecf796f89f0e51eb750b445a85e332bf750a Mon Sep 17 00:00:00 2001 From: KungFuDonkey <[email protected]> Date: Sat, 15 Nov 2025 14:09:12 +0100 Subject: [PATCH 05/13] Fix uint64_t and builtin tests --- clang/lib/CodeGen/CGHLSLBuiltins.cpp | 2 +- clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl | 9 --------- .../test/SemaHLSL/BuiltIns/WaveActiveBitOr-errors.hlsl | 10 +++++----- 3 files changed, 6 insertions(+), 15 deletions(-) diff --git a/clang/lib/CodeGen/CGHLSLBuiltins.cpp b/clang/lib/CodeGen/CGHLSLBuiltins.cpp index 3660214b31552..0843e128d74f9 100644 --- a/clang/lib/CodeGen/CGHLSLBuiltins.cpp +++ b/clang/lib/CodeGen/CGHLSLBuiltins.cpp @@ -788,7 +788,7 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, } case Builtin::BI__builtin_hlsl_wave_active_bit_or: { Value *Op = EmitScalarExpr(E->getArg(0)); - assert(Op->getType()->hasUnsignedIntegerRepresentation() && + assert(E->getArg(0)->getType()->hasUnsignedIntegerRepresentation() && "Intrinsic WaveActiveBitOr operand must have a unsigned integer representation"); Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveActiveBitOrIntrinsic(); diff --git a/clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl b/clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl index cfb3d2514cdde..8741c1eccd8a1 100644 --- a/clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl +++ b/clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl @@ -20,12 +20,3 @@ uint test_uint(uint expr) { } // CHECK: declare [[TY]] @llvm.[[ICF]].wave.reduce.or.i32([[TY]]) #[[#attr:]] - -// CHECK-LABEL: test_uint64_t -uint64_t test_uint64_t(uint64_t expr) { - // CHECK: %[[RET:.*]] = call i1 [[TY:.*]] @llvm.[[ICF]].wave.reduce.or.i64([[TY]] %[[#]]) - // CHECK: ret [[TY]] %[[RET]] - return WaveActiveBitOr(expr); -} - -// CHECK: declare [[TY]] @llvm.[[ICF]].wave.reduce.or.i64([[TY]]) #[[#attr:]] diff --git a/clang/test/SemaHLSL/BuiltIns/WaveActiveBitOr-errors.hlsl b/clang/test/SemaHLSL/BuiltIns/WaveActiveBitOr-errors.hlsl index 8eb62c7d96b4e..3b8e6f29bb48a 100644 --- a/clang/test/SemaHLSL/BuiltIns/WaveActiveBitOr-errors.hlsl +++ b/clang/test/SemaHLSL/BuiltIns/WaveActiveBitOr-errors.hlsl @@ -10,29 +10,29 @@ uint2 test_too_many_arg(uint2 p0) { // expected-error@-1 {{too many arguments to function call, expected 1, have 2}} } -bool test_expr_bool_type_check(bool p0) { +uint test_expr_bool_type_check(bool p0) { return __builtin_hlsl_wave_active_bit_or(p0); // expected-error@-1 {{invalid operand of type 'bool'}} } -float test_expr_float_type_check(float p0) { +uint test_expr_float_type_check(float p0) { return __builtin_hlsl_wave_active_bit_or(p0); // expected-error@-1 {{invalid operand of type 'float'}} } -bool2 test_expr_bool_vec_type_check(bool2 p0) { +uint2 test_expr_bool_vec_type_check(bool2 p0) { return __builtin_hlsl_wave_active_bit_or(p0); // expected-error@-1 {{invalid operand of type 'bool2' (aka 'vector<bool, 2>')}} } -float2 test_expr_float_type_check(float2 p0) { +uint2 test_expr_float_type_check(float2 p0) { return __builtin_hlsl_wave_active_bit_or(p0); // expected-error@-1 {{invalid operand of type 'float2' (aka 'vector<float, 2>')}} } struct S { float f; }; -S test_expr_struct_type_check(S p0) { +uint test_expr_struct_type_check(S p0) { return __builtin_hlsl_wave_active_bit_or(p0); // expected-error@-1 {{invalid operand of type 'S' where a scalar or vector is required}} } >From 165e9bc10ab437b57817d25e18928a514d47f950 Mon Sep 17 00:00:00 2001 From: KungFuDonkey <[email protected]> Date: Sat, 22 Nov 2025 15:55:35 +0100 Subject: [PATCH 06/13] readded 64 bit test --- .../CodeGenHLSL/builtins/WaveActiveBitOr.hlsl | 17 ++++++++++++----- .../AArch64/AArch64MachineFunctionInfo.cpp | 2 ++ 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl b/clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl index 8741c1eccd8a1..e9db6254ac520 100644 --- a/clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl +++ b/clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl @@ -6,17 +6,24 @@ // RUN: spirv-pc-vulkan-compute %s -emit-llvm -disable-llvm-passes -o - | \ // RUN: FileCheck %s --check-prefixes=CHECK,SPVCHECK -// DXCHECK: define hidden [[FN_TYPE:]]noundef i1 @ -// SPVCHECK: define hidden [[FN_TYPE:spir_func ]]noundef i1 @ - // Test basic lowering to runtime function call. // CHECK-LABEL: test_uint uint test_uint(uint expr) { - // DXCHECK: %[[RET:.*]] = call i1 [[TY:.*]] @llvm.[[ICF:dx]].wave.reduce.or.i32([[TY]] %[[#]]) - // SPVCHECK: %[[RET:.*]] = call i1 [[TY:.*]] @llvm.[[ICF:spv]].wave.reduce.or.i32([[TY]] %[[#]]) + // DXCHECK: %[[RET:.*]] = call [[TY:.*]] @llvm.[[ICF:dx]].wave.reduce.or.i32([[TY]] %[[#]]) + // SPVCHECK: %[[RET:.*]] = call [[TY:.*]] @llvm.[[ICF:spv]].wave.reduce.or.i32([[TY]] %[[#]]) // CHECK: ret [[TY]] %[[RET]] return WaveActiveBitOr(expr); } // CHECK: declare [[TY]] @llvm.[[ICF]].wave.reduce.or.i32([[TY]]) #[[#attr:]] + +// CHECK-LABEL: test_uint64_t +uint64_t test_uint64_t(uint64_t expr) { + // DXCHECK: %[[RET:.*]] = call [[TY:.*]] @llvm.[[ICF:dx]].wave.reduce.or.i64([[TY]] %[[#]]) + // SPVCHECK: %[[RET:.*]] = call [[TY:.*]] @llvm.[[ICF:spv]].wave.reduce.or.i64([[TY]] %[[#]]) + // CHECK: ret [[TY]] %[[RET]] + return WaveActiveBitOr(expr); +} + +// CHECK: declare [[TY]] @llvm.[[ICF]].wave.reduce.or.i64([[TY]]) #[[#attr:]] diff --git a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp index d6d63f3b6198d..4ed15eb40756a 100644 --- a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp @@ -182,6 +182,8 @@ bool AArch64FunctionInfo::shouldSignReturnAddress(SignReturnAddress Condition, return IsLRSpilled; case SignReturnAddress::All: return true; + default: + return false; } } >From 0399f3c0ce97decac58d0425d1d7aa952a0c0bc7 Mon Sep 17 00:00:00 2001 From: KungFuDonkey <[email protected]> Date: Sat, 22 Nov 2025 16:05:04 +0100 Subject: [PATCH 07/13] removed fix for aarch64machine compilation error --- llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp | 2 -- 1 file changed, 2 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp index 4ed15eb40756a..d6d63f3b6198d 100644 --- a/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.cpp @@ -182,8 +182,6 @@ bool AArch64FunctionInfo::shouldSignReturnAddress(SignReturnAddress Condition, return IsLRSpilled; case SignReturnAddress::All: return true; - default: - return false; } } >From 495bdaa888bf3a01f874dcbd78d272e78f7a7a90 Mon Sep 17 00:00:00 2001 From: KungFuDonkey <[email protected]> Date: Sun, 23 Nov 2025 15:31:21 +0100 Subject: [PATCH 08/13] fixed tablegen mis indexing arguments and finally able to run tests locally --- clang/include/clang/Basic/Builtins.td | 2 +- clang/lib/CodeGen/CGHLSLBuiltins.cpp | 5 +-- .../CodeGenHLSL/builtins/WaveActiveBitOr.hlsl | 4 +-- .../BuiltIns/WaveActiveBitOr-errors.hlsl | 31 +++++-------------- llvm/include/llvm/IR/IntrinsicsDirectX.td | 2 +- llvm/include/llvm/IR/IntrinsicsSPIRV.td | 2 +- 6 files changed, 15 insertions(+), 31 deletions(-) diff --git a/clang/include/clang/Basic/Builtins.td b/clang/include/clang/Basic/Builtins.td index 9761a212b8284..e1c40bd68fd83 100644 --- a/clang/include/clang/Basic/Builtins.td +++ b/clang/include/clang/Basic/Builtins.td @@ -5039,7 +5039,7 @@ def HLSLWaveActiveAnyTrue : LangBuiltin<"HLSL_LANG"> { def HLSLWaveActiveBitOr : LangBuiltin<"HLSL_LANG"> { let Spellings = ["__builtin_hlsl_wave_active_bit_or"]; let Attributes = [NoThrow, Const]; - let Prototype = "void (...)"; + let Prototype = "unsigned int (unsigned int)"; } def HLSLWaveActiveCountBits : LangBuiltin<"HLSL_LANG"> { diff --git a/clang/lib/CodeGen/CGHLSLBuiltins.cpp b/clang/lib/CodeGen/CGHLSLBuiltins.cpp index 6fe33f37955f8..93797f79276e7 100644 --- a/clang/lib/CodeGen/CGHLSLBuiltins.cpp +++ b/clang/lib/CodeGen/CGHLSLBuiltins.cpp @@ -835,8 +835,9 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, "Intrinsic WaveActiveBitOr operand must have a unsigned integer representation"); Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveActiveBitOrIntrinsic(); - return EmitRuntimeCall( - Intrinsic::getOrInsertDeclaration(&CGM.getModule(), ID), {Op}); + return EmitRuntimeCall(Intrinsic::getOrInsertDeclaration( + &CGM.getModule(), ID, {Op->getType()}), + ArrayRef{Op}, "hlsl.wave.active.bit.or"); } case Builtin::BI__builtin_hlsl_wave_active_count_bits: { Value *OpExpr = EmitScalarExpr(E->getArg(0)); diff --git a/clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl b/clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl index e9db6254ac520..7ba36766b6f04 100644 --- a/clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl +++ b/clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl @@ -11,7 +11,7 @@ // CHECK-LABEL: test_uint uint test_uint(uint expr) { // DXCHECK: %[[RET:.*]] = call [[TY:.*]] @llvm.[[ICF:dx]].wave.reduce.or.i32([[TY]] %[[#]]) - // SPVCHECK: %[[RET:.*]] = call [[TY:.*]] @llvm.[[ICF:spv]].wave.reduce.or.i32([[TY]] %[[#]]) + // SPVCHECK: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.[[ICF:spv]].wave.reduce.or.i32([[TY]] %[[#]]) // CHECK: ret [[TY]] %[[RET]] return WaveActiveBitOr(expr); } @@ -21,7 +21,7 @@ uint test_uint(uint expr) { // CHECK-LABEL: test_uint64_t uint64_t test_uint64_t(uint64_t expr) { // DXCHECK: %[[RET:.*]] = call [[TY:.*]] @llvm.[[ICF:dx]].wave.reduce.or.i64([[TY]] %[[#]]) - // SPVCHECK: %[[RET:.*]] = call [[TY:.*]] @llvm.[[ICF:spv]].wave.reduce.or.i64([[TY]] %[[#]]) + // SPVCHECK: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.[[ICF:spv]].wave.reduce.or.i64([[TY]] %[[#]]) // CHECK: ret [[TY]] %[[RET]] return WaveActiveBitOr(expr); } diff --git a/clang/test/SemaHLSL/BuiltIns/WaveActiveBitOr-errors.hlsl b/clang/test/SemaHLSL/BuiltIns/WaveActiveBitOr-errors.hlsl index 3b8e6f29bb48a..de40e5bdb45f6 100644 --- a/clang/test/SemaHLSL/BuiltIns/WaveActiveBitOr-errors.hlsl +++ b/clang/test/SemaHLSL/BuiltIns/WaveActiveBitOr-errors.hlsl @@ -5,34 +5,17 @@ uint test_too_few_arg() { // expected-error@-1 {{too few arguments to function call, expected 1, have 0}} } -uint2 test_too_many_arg(uint2 p0) { +uint test_too_many_arg(uint p0) { return __builtin_hlsl_wave_active_bit_or(p0, p0); // expected-error@-1 {{too many arguments to function call, expected 1, have 2}} } -uint test_expr_bool_type_check(bool p0) { - return __builtin_hlsl_wave_active_bit_or(p0); - // expected-error@-1 {{invalid operand of type 'bool'}} -} - -uint test_expr_float_type_check(float p0) { - return __builtin_hlsl_wave_active_bit_or(p0); - // expected-error@-1 {{invalid operand of type 'float'}} -} - -uint2 test_expr_bool_vec_type_check(bool2 p0) { - return __builtin_hlsl_wave_active_bit_or(p0); - // expected-error@-1 {{invalid operand of type 'bool2' (aka 'vector<bool, 2>')}} -} - -uint2 test_expr_float_type_check(float2 p0) { - return __builtin_hlsl_wave_active_bit_or(p0); - // expected-error@-1 {{invalid operand of type 'float2' (aka 'vector<float, 2>')}} -} - -struct S { float f; }; +struct Foo +{ + int a; +}; -uint test_expr_struct_type_check(S p0) { +uint test_type_check(Foo p0) { return __builtin_hlsl_wave_active_bit_or(p0); - // expected-error@-1 {{invalid operand of type 'S' where a scalar or vector is required}} + // expected-error@-1 {{no viable conversion from 'Foo' to 'unsigned int'}} } diff --git a/llvm/include/llvm/IR/IntrinsicsDirectX.td b/llvm/include/llvm/IR/IntrinsicsDirectX.td index c5e2e24051877..e7889faf6e3a8 100644 --- a/llvm/include/llvm/IR/IntrinsicsDirectX.td +++ b/llvm/include/llvm/IR/IntrinsicsDirectX.td @@ -154,7 +154,7 @@ def int_dx_wave_active_countbits : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i1 def int_dx_wave_all : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>; def int_dx_wave_any : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>; def int_dx_wave_getlaneindex : DefaultAttrsIntrinsic<[llvm_i32_ty], [], [IntrConvergent, IntrNoMem]>; -def int_dx_wave_reduce_or : DefaultAttrsIntrinsic<[llvm_anyint_ty], [llvm_anyint_ty], [IntrConvergent, IntrNoMem]>; +def int_dx_wave_reduce_or : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; def int_dx_wave_reduce_max : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; def int_dx_wave_reduce_umax : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; def int_dx_wave_reduce_min : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td index 93a26b4bcaef9..1c791ee8f2297 100644 --- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td +++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td @@ -120,7 +120,7 @@ def int_spv_rsqrt : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty] def int_spv_wave_active_countbits : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>; def int_spv_wave_all : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>; def int_spv_wave_any : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_i1_ty], [IntrConvergent, IntrNoMem]>; - def int_spv_wave_reduce_or : DefaultAttrsIntrinsic<[llvm_anyint_ty], [llvm_anyint_ty], [IntrConvergent, IntrNoMem]>; + def int_spv_wave_reduce_or : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; def int_spv_wave_reduce_umax : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; def int_spv_wave_reduce_max : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; def int_spv_wave_reduce_min : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; >From d034a8b1b9df1c0ad7657856d2eaa60781198585 Mon Sep 17 00:00:00 2001 From: KungFuDonkey <[email protected]> Date: Sun, 23 Nov 2025 17:12:45 +0100 Subject: [PATCH 09/13] clang format --- clang/lib/CodeGen/CGHLSLBuiltins.cpp | 3 ++- llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp | 5 +++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/clang/lib/CodeGen/CGHLSLBuiltins.cpp b/clang/lib/CodeGen/CGHLSLBuiltins.cpp index 93797f79276e7..7969eabc206e4 100644 --- a/clang/lib/CodeGen/CGHLSLBuiltins.cpp +++ b/clang/lib/CodeGen/CGHLSLBuiltins.cpp @@ -832,7 +832,8 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, case Builtin::BI__builtin_hlsl_wave_active_bit_or: { Value *Op = EmitScalarExpr(E->getArg(0)); assert(E->getArg(0)->getType()->hasUnsignedIntegerRepresentation() && - "Intrinsic WaveActiveBitOr operand must have a unsigned integer representation"); + "Intrinsic WaveActiveBitOr operand must have a unsigned integer " + "representation"); Intrinsic::ID ID = CGM.getHLSLRuntime().getWaveActiveBitOrIntrinsic(); return EmitRuntimeCall(Intrinsic::getOrInsertDeclaration( diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp index d4514143be3a8..de7b0c3c14280 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp @@ -2443,8 +2443,9 @@ bool SPIRVInstructionSelector::selectWaveActiveCountBits( return Result; } -bool SPIRVInstructionSelector::selectWaveReduceOr( - Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const { +bool SPIRVInstructionSelector::selectWaveReduceOr(Register ResVReg, + const SPIRVType *ResType, + MachineInstr &I) const { assert(I.getNumOperands() == 3); assert(I.getOperand(2).isReg()); >From ea8588cb2cf8afc6893677e640530cb1b5509596 Mon Sep 17 00:00:00 2001 From: KungFuDonkey <[email protected]> Date: Sun, 23 Nov 2025 17:16:12 +0100 Subject: [PATCH 10/13] clang format --- clang/lib/Sema/SemaHLSL.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/lib/Sema/SemaHLSL.cpp b/clang/lib/Sema/SemaHLSL.cpp index daa2625ce7ae0..5e48996d23cac 100644 --- a/clang/lib/Sema/SemaHLSL.cpp +++ b/clang/lib/Sema/SemaHLSL.cpp @@ -3332,7 +3332,7 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { QualType ArgTyExpr = Expr.get()->getType(); auto *VTy = ArgTyExpr->getAs<VectorType>(); if (!(ArgTyExpr->isIntegerType() || - (VTy && VTy->getElementType()->isIntegerType()))) { + (VTy && VTy->getElementType()->isIntegerType()))) { SemaRef.Diag(TheCall->getArg(0)->getBeginLoc(), diag::err_builtin_invalid_arg_type) << ArgTyExpr << SemaRef.Context.UnsignedIntTy << 1 << 0 << 0; >From a2dc315e487d5ddc34bc86f889aaee0308552a59 Mon Sep 17 00:00:00 2001 From: KungFuDonkey <[email protected]> Date: Sat, 7 Feb 2026 13:17:38 +0100 Subject: [PATCH 11/13] added vector tests, float test and updated other comments --- .../lib/Headers/hlsl/hlsl_alias_intrinsics.h | 5 +- .../CodeGenHLSL/builtins/WaveActiveBitOr.hlsl | 60 ++++++++++++++ .../BuiltIns/WaveActiveBitOr-errors.hlsl | 5 ++ .../Target/SPIRV/SPIRVInstructionSelector.cpp | 80 +++++++++---------- 4 files changed, 108 insertions(+), 42 deletions(-) diff --git a/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h b/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h index 426666159650d..e781c2a95e7dc 100644 --- a/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h +++ b/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h @@ -2591,8 +2591,9 @@ __attribute__((convergent)) double4 WaveReadLaneAt(double4, uint32_t); // WaveActiveBitOr builtins //===----------------------------------------------------------------------===// -// \brief Returns the value of the expression for the given lane index within -// the specified wave. +// \brief Returns the bitwise OR of all the values of <expr> across all active +// non-helper lanes in the current wave, and replicates it back to +// all active non-helper lanes. _HLSL_AVAILABILITY(shadermodel, 6.0) _HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_bit_or) diff --git a/clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl b/clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl index 7ba36766b6f04..eb633ae3d16db 100644 --- a/clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl +++ b/clang/test/CodeGenHLSL/builtins/WaveActiveBitOr.hlsl @@ -18,6 +18,36 @@ uint test_uint(uint expr) { // CHECK: declare [[TY]] @llvm.[[ICF]].wave.reduce.or.i32([[TY]]) #[[#attr:]] +// CHECK-LABEL: test_uint2 +uint2 test_uint2(uint2 expr) { + // DXCHECK: %[[RET:.*]] = call [[TY:.*]] @llvm.[[ICF:dx]].wave.reduce.or.v2i32([[TY]] %[[#]]) + // SPVCHECK: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.[[ICF:spv]].wave.reduce.or.v2i32([[TY]] %[[#]]) + // CHECK: ret [[TY]] %[[RET]] + return WaveActiveBitOr(expr); +} + +// CHECK: declare [[TY]] @llvm.[[ICF]].wave.reduce.or.v2i32([[TY]]) #[[#attr:]] + +// CHECK-LABEL: test_uint3 +uint3 test_uint3(uint3 expr) { + // DXCHECK: %[[RET:.*]] = call [[TY:.*]] @llvm.[[ICF:dx]].wave.reduce.or.v3i32([[TY]] %[[#]]) + // SPVCHECK: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.[[ICF:spv]].wave.reduce.or.v3i32([[TY]] %[[#]]) + // CHECK: ret [[TY]] %[[RET]] + return WaveActiveBitOr(expr); +} + +// CHECK: declare [[TY]] @llvm.[[ICF]].wave.reduce.or.v3i32([[TY]]) #[[#attr:]] + +// CHECK-LABEL: test_uint4 +uint4 test_uint4(uint4 expr) { + // DXCHECK: %[[RET:.*]] = call [[TY:.*]] @llvm.[[ICF:dx]].wave.reduce.or.v4i32([[TY]] %[[#]]) + // SPVCHECK: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.[[ICF:spv]].wave.reduce.or.v4i32([[TY]] %[[#]]) + // CHECK: ret [[TY]] %[[RET]] + return WaveActiveBitOr(expr); +} + +// CHECK: declare [[TY]] @llvm.[[ICF]].wave.reduce.or.v4i32([[TY]]) #[[#attr:]] + // CHECK-LABEL: test_uint64_t uint64_t test_uint64_t(uint64_t expr) { // DXCHECK: %[[RET:.*]] = call [[TY:.*]] @llvm.[[ICF:dx]].wave.reduce.or.i64([[TY]] %[[#]]) @@ -27,3 +57,33 @@ uint64_t test_uint64_t(uint64_t expr) { } // CHECK: declare [[TY]] @llvm.[[ICF]].wave.reduce.or.i64([[TY]]) #[[#attr:]] + +// CHECK-LABEL: test_uint64_t2 +uint64_t2 test_uint64_t(uint64_t2 expr) { + // DXCHECK: %[[RET:.*]] = call [[TY:.*]] @llvm.[[ICF:dx]].wave.reduce.or.v2i64([[TY]] %[[#]]) + // SPVCHECK: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.[[ICF:spv]].wave.reduce.or.v2i64([[TY]] %[[#]]) + // CHECK: ret [[TY]] %[[RET]] + return WaveActiveBitOr(expr); +} + +// CHECK: declare [[TY]] @llvm.[[ICF]].wave.reduce.or.v2i64([[TY]]) #[[#attr:]] + +// CHECK-LABEL: test_uint64_t3 +uint64_t3 test_uint64_t(uint64_t3 expr) { + // DXCHECK: %[[RET:.*]] = call [[TY:.*]] @llvm.[[ICF:dx]].wave.reduce.or.v3i64([[TY]] %[[#]]) + // SPVCHECK: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.[[ICF:spv]].wave.reduce.or.v3i64([[TY]] %[[#]]) + // CHECK: ret [[TY]] %[[RET]] + return WaveActiveBitOr(expr); +} + +// CHECK: declare [[TY]] @llvm.[[ICF]].wave.reduce.or.v3i64([[TY]]) #[[#attr:]] + +// CHECK-LABEL: test_uint64_t4 +uint64_t4 test_uint64_t4(uint64_t4 expr) { + // DXCHECK: %[[RET:.*]] = call [[TY:.*]] @llvm.[[ICF:dx]].wave.reduce.or.v4i64([[TY]] %[[#]]) + // SPVCHECK: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.[[ICF:spv]].wave.reduce.or.v4i64([[TY]] %[[#]]) + // CHECK: ret [[TY]] %[[RET]] + return WaveActiveBitOr(expr); +} + +// CHECK: declare [[TY]] @llvm.[[ICF]].wave.reduce.or.v4i64([[TY]]) #[[#attr:]] diff --git a/clang/test/SemaHLSL/BuiltIns/WaveActiveBitOr-errors.hlsl b/clang/test/SemaHLSL/BuiltIns/WaveActiveBitOr-errors.hlsl index de40e5bdb45f6..73479c39e2e2f 100644 --- a/clang/test/SemaHLSL/BuiltIns/WaveActiveBitOr-errors.hlsl +++ b/clang/test/SemaHLSL/BuiltIns/WaveActiveBitOr-errors.hlsl @@ -19,3 +19,8 @@ uint test_type_check(Foo p0) { return __builtin_hlsl_wave_active_bit_or(p0); // expected-error@-1 {{no viable conversion from 'Foo' to 'unsigned int'}} } + +float test_expr_bool_type_check(float p0) { + return __builtin_hlsl_wave_active_bit_or(p0); + // expected-error@-1 {{1st argument must be a scalar or vector of integer types (was 'float')}} +} diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp index 773dd86eeef38..1c91c37ffdfd5 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp @@ -1874,15 +1874,15 @@ bool SPIRVInstructionSelector::selectAtomicRMW(Register ResVReg, ValueReg = TmpReg; } - BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(NewOpcode)) - .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(Ptr) - .addUse(ScopeReg) - .addUse(MemSemReg) - .addUse(ValueReg) - .constrainAllUses(TII, TRI, RBI); - return true; + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(NewOpcode)) + .addDef(ResVReg) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(Ptr) + .addUse(ScopeReg) + .addUse(MemSemReg) + .addUse(ValueReg) + .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectUnmergeValues(MachineInstr &I) const { @@ -2531,12 +2531,12 @@ bool SPIRVInstructionSelector::selectIntegerDotExpansion( for (unsigned i = 1; i < GR.getScalarOrVectorComponentCount(VecType); i++) { Register Elt = MRI->createVirtualRegister(GR.getRegClass(ResType)); - BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract)) - .addDef(Elt) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(TmpVec) - .addImm(i) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract)) + .addDef(Elt) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(TmpVec) + .addImm(i) + .constrainAllUses(TII, TRI, RBI); Register Sum = i < GR.getScalarOrVectorComponentCount(VecType) - 1 ? MRI->createVirtualRegister(GR.getRegClass(ResType)) @@ -2737,13 +2737,13 @@ bool SPIRVInstructionSelector::selectSign(Register ResVReg, ? MRI->createVirtualRegister(&SPIRV::IDRegClass) : ResVReg; - BuildMI(BB, I, DL, TII.get(SPIRV::OpExtInst)) - .addDef(SignReg) - .addUse(GR.getSPIRVTypeID(InputType)) - .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450)) - .addImm(SignOpcode) - .addUse(InputRegister) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, DL, TII.get(SPIRV::OpExtInst)) + .addDef(SignReg) + .addUse(GR.getSPIRVTypeID(InputType)) + .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450)) + .addImm(SignOpcode) + .addUse(InputRegister) + .constrainAllUses(TII, TRI, RBI); if (NeedsConversion) { auto ConvertOpcode = IsFloatTy ? SPIRV::OpConvertFToS : SPIRV::OpSConvert; @@ -2802,7 +2802,6 @@ bool SPIRVInstructionSelector::selectWaveActiveCountBits( return true; } - bool SPIRVInstructionSelector::selectWavePrefixBitCount( Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const { @@ -3681,22 +3680,22 @@ bool SPIRVInstructionSelector::selectDerivativeInst( Register ConvertToVReg = MRI->createVirtualRegister(RegClass); Register DpdOpVReg = MRI->createVirtualRegister(RegClass); - BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpFConvert)) - .addDef(ConvertToVReg) - .addUse(GR.getSPIRVTypeID(F32ConvertTy)) - .addUse(SrcReg) - .constrainAllUses(TII, TRI, RBI); - BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(DPdOpCode)) - .addDef(DpdOpVReg) - .addUse(GR.getSPIRVTypeID(F32ConvertTy)) - .addUse(ConvertToVReg) - .constrainAllUses(TII, TRI, RBI); - BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpFConvert)) - .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(DpdOpVReg) - .constrainAllUses(TII, TRI, RBI); - return true; + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpFConvert)) + .addDef(ConvertToVReg) + .addUse(GR.getSPIRVTypeID(F32ConvertTy)) + .addUse(SrcReg) + .constrainAllUses(TII, TRI, RBI); + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(DPdOpCode)) + .addDef(DpdOpVReg) + .addUse(GR.getSPIRVTypeID(F32ConvertTy)) + .addUse(ConvertToVReg) + .constrainAllUses(TII, TRI, RBI); + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpFConvert)) + .addDef(ResVReg) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(DpdOpVReg) + .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, @@ -4056,7 +4055,8 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, case Intrinsic::spv_wave_is_first_lane: return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformElect); case Intrinsic::spv_wave_reduce_or: - return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformBitwiseOr); + return selectWaveOpInst(ResVReg, ResType, I, + SPIRV::OpGroupNonUniformBitwiseOr); case Intrinsic::spv_wave_reduce_umax: return selectWaveReduceMax(ResVReg, ResType, I, /*IsUnsigned*/ true); case Intrinsic::spv_wave_reduce_max: >From 714d737f686a4b4c887593c52ca5c3d146c1fac8 Mon Sep 17 00:00:00 2001 From: KungFuDonkey <[email protected]> Date: Sat, 7 Feb 2026 13:23:52 +0100 Subject: [PATCH 12/13] Reset basic builtins --- clang/include/clang/Basic/Builtins.td | 285 +++++++++++--------------- 1 file changed, 119 insertions(+), 166 deletions(-) diff --git a/clang/include/clang/Basic/Builtins.td b/clang/include/clang/Basic/Builtins.td index b4acc07fd4cd5..05e3af4a0e96f 100644 --- a/clang/include/clang/Basic/Builtins.td +++ b/clang/include/clang/Basic/Builtins.td @@ -8,64 +8,68 @@ include "clang/Basic/BuiltinsBase.td" -class FPMathTemplate - : Template<["float", "double", "long double"], ["f", "", "l"]>; +class FPMathTemplate : Template<["float", "double", "long double"], + ["f", "", "l"]>; -class FPMathWithF16Template - : Template<["float", "double", "long double", "__fp16"], ["f", "", "l", - "f16"]>; +class FPMathWithF16Template : + Template<["float", "double", "long double", "__fp16"], + ["f", "", "l", "f16"]>; -class FPMathWithF16F128Template - : Template<["float", "double", "long double", "__fp16", "__float128"], - ["f", "", "l", "f16", "f128"]>; +class FPMathWithF16F128Template : + Template<["float", "double", "long double", "__fp16", "__float128"], + ["f", "", "l", "f16", "f128"]>; -class FPMathWithF128Template - : Template<["float", "double", "long double", "__float128"], ["f", "", "l", - "f128"]>; +class FPMathWithF128Template : + Template<["float", "double", "long double", "__float128"], + ["f", "", "l", "f128"]>; -class F16F128MathTemplate : Template<["__fp16", "__float128"], ["f16", "f128"]>; +class F16F128MathTemplate : Template<["__fp16", "__float128"], + ["f16", "f128"]>; -class IntMathTemplate - : Template<["int", "long int", "long long int"], ["", "l", "ll"], - /*AsPrefix=*/1>; +class IntMathTemplate : Template<["int", "long int", "long long int"], + ["", "l", "ll"], /*AsPrefix=*/1>; -class MSInt8_16_32Template - : Template<["char", "short", "msint32_t"], ["8", "16", ""]>; +class MSInt8_16_32Template : Template<["char", "short", "msint32_t"], + ["8", "16", ""]>; class Int8_16_32_64Template - : Template<["char", "short", "int", "long long int"], ["8", "16", "32", - "64"]>; + : Template<["char", "short", "int", "long long int"], + ["8", "16", "32", "64"]>; class MSInt8_16_32_64Template - : Template<["char", "short", "msint32_t", "long long int"], ["8", "16", "", - "64"]>; + : Template<["char", "short", "msint32_t", "long long int"], + ["8", "16", "", "64"]>; -class MSInt16_32Template : Template<["short", "msint32_t"], ["16", ""]>; +class MSInt16_32Template : Template<["short", "msint32_t"], + ["16", ""]>; -class MSUInt16_32_64Template - : Template<["unsigned short", "unsigned int", "uint64_t"], ["16", "", - "64"]>; +class MSUInt16_32_64Template : + Template<["unsigned short", "unsigned int", "uint64_t"], + ["16", "", "64"]>; -class MSInt32_64Template : Template<["msint32_t", "int64_t"], ["", "64"]>; +class MSInt32_64Template : Template<["msint32_t", "int64_t"], + ["", "64"]>; -class FloatDoubleTemplate : Template<["float", "double"], ["f", ""]>; +class FloatDoubleTemplate : Template<["float", "double"], + ["f", ""]>; // FIXME: These assume that char -> i8, short -> i16, int -> i32, // long long -> i64. -class SyncBuiltinsTemplate - : Template<["char", "short", "int", "long long int", "__int128_t"], - ["1", "2", "4", "8", "16"]>; +class SyncBuiltinsTemplate : + Template<["char", "short", "int", "long long int", "__int128_t"], + ["1", "2", "4", "8", "16"]>; -class BitInt8_16_32_64BuiltinsTemplate - : Template<["unsigned char", "unsigned short", "uint32_t", "uint64_t"], - ["8", "16", "32", "64"]>; +class BitInt8_16_32_64BuiltinsTemplate : + Template<["unsigned char", "unsigned short", "uint32_t", "uint64_t"], + ["8", "16", "32", "64"]>; -class BitShort_Int_Long_LongLongTemplate - : Template<["short", "int", "long int", "long long int"], ["s", "", "l", - "ll"]>; +class BitShort_Int_Long_LongLongTemplate : + Template<["short", "int", "long int", "long long int"], + ["s", "", "l", "ll"]>; -class BitInt_Long_LongLongTemplate - : Template<["int", "long int", "long long int"], ["", "l", "ll"]>; +class BitInt_Long_LongLongTemplate : + Template<["int", "long int", "long long int"], + ["", "l", "ll"]>; // Most of the types used in the prototypes are types from C, C++ or ObjC. There // are a few builtin-specific types and qualifiers. @@ -135,64 +139,55 @@ def CeilF16F128 : Builtin, F16F128MathTemplate { def CosF16F128 : Builtin, F16F128MathTemplate { let Spellings = ["__builtin_cos"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "T(T)"; } def CoshF16F128 : Builtin, F16F128MathTemplate { let Spellings = ["__builtin_cosh"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "T(T)"; } def ErfF128 : Builtin { let Spellings = ["__builtin_erff128"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "__float128(__float128)"; } def ErfcF128 : Builtin { let Spellings = ["__builtin_erfcf128"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "__float128(__float128)"; } def ExpF16F128 : Builtin, F16F128MathTemplate { let Spellings = ["__builtin_exp"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "T(T)"; } def Exp2F16F128 : Builtin, F16F128MathTemplate { let Spellings = ["__builtin_exp2"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "T(T)"; } def Exp10F16F128 : Builtin, F16F128MathTemplate { let Spellings = ["__builtin_exp10"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "T(T)"; } def Expm1F128 : Builtin { let Spellings = ["__builtin_expm1f128"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "__float128(__float128)"; } def FdimF128 : Builtin { let Spellings = ["__builtin_fdimf128"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "__float128(__float128, __float128)"; } @@ -204,8 +199,7 @@ def FloorF16F128 : Builtin, F16F128MathTemplate { def FmaF16F128 : Builtin, F16F128MathTemplate { let Spellings = ["__builtin_fma"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "T(T, T, T)"; } @@ -235,8 +229,7 @@ def FminimumNumF16F128 : Builtin, F16F128MathTemplate { def Atan2F16F128 : Builtin, F16F128MathTemplate { let Spellings = ["__builtin_atan2"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "T(T, T)"; } @@ -266,8 +259,7 @@ def FabsF128 : Builtin { def FmodF16F128 : F16F128MathTemplate, Builtin { let Spellings = ["__builtin_fmod"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "T(T, T)"; } @@ -284,7 +276,7 @@ def HugeVal : Builtin, FPMathWithF128Template { } def HugeValF16 : Builtin { - let Spellings = ["__builtin_huge_valf16"]; + let Spellings = ["__builtin_huge_valf16"]; let Attributes = [NoThrow, Const, Constexpr]; let Prototype = "_Float16()"; } @@ -303,8 +295,7 @@ def InfF16 : Builtin { def LdexpF16F128 : F16F128MathTemplate, Builtin { let Spellings = ["__builtin_ldexp"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "T(T, int)"; } @@ -328,10 +319,9 @@ def NanF128 : Builtin { let Prototype = "__float128(char const*)"; } -def Nans - : Builtin, - Template<["float", "double", "long double", "_Float16", "__float128"], - ["f", "", "l", "f16", "f128"]> { +def Nans : Builtin, + Template<["float", "double", "long double", "_Float16", "__float128"], + ["f", "", "l", "f16", "f128"]> { let Spellings = ["__builtin_nans"]; let Attributes = [FunctionWithBuiltinPrefix, NoThrow, Pure, Constexpr]; let Prototype = "T(char const*)"; @@ -345,22 +335,19 @@ def PowI : Builtin, FPMathTemplate { def PowF16F128 : Builtin, F16F128MathTemplate { let Spellings = ["__builtin_pow"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "T(T, T)"; } def HypotF128 : Builtin { let Spellings = ["__builtin_hypotf128"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "__float128(__float128, __float128)"; } def ILogbF128 : Builtin { let Spellings = ["__builtin_ilogbf128"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "int(__float128)"; } @@ -372,64 +359,55 @@ def LgammaF128 : Builtin { def LLrintF128 : Builtin { let Spellings = ["__builtin_llrintf128"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "long long int(__float128)"; } def LLroundF128 : Builtin { let Spellings = ["__builtin_llroundf128"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "long long int(__float128)"; } def Log10F16F128 : Builtin, F16F128MathTemplate { let Spellings = ["__builtin_log10"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "T(T)"; } def Log1pF128 : Builtin { let Spellings = ["__builtin_log1pf128"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "__float128(__float128)"; } def Log2F16F128 : Builtin, F16F128MathTemplate { let Spellings = ["__builtin_log2"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "T(T)"; } def LogbF128 : Builtin { let Spellings = ["__builtin_logbf128"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "__float128(__float128)"; } def LogF16F128 : Builtin, F16F128MathTemplate { let Spellings = ["__builtin_log"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "T(T)"; } def LrintF128 : Builtin { let Spellings = ["__builtin_lrintf128"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "long int(__float128)"; } def LroundF128 : Builtin { let Spellings = ["__builtin_lroundf128"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "long int(__float128)"; } @@ -441,22 +419,19 @@ def NearbyintF128 : Builtin { def NextafterF128 : Builtin { let Spellings = ["__builtin_nextafterf128"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "__float128(__float128, __float128)"; } def NexttowardF128 : Builtin { let Spellings = ["__builtin_nexttowardf128"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "__float128(__float128, __float128)"; } def RemainderF128 : Builtin { let Spellings = ["__builtin_remainderf128"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, - ConstIgnoringErrnoAndExceptions]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, ConstIgnoringErrnoAndExceptions]; let Prototype = "__float128(__float128, __float128)"; } @@ -695,13 +670,15 @@ def Signbit : Builtin { def SignbitF : Builtin { let Spellings = ["__builtin_signbitf"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, Const, Constexpr]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, Const, + Constexpr]; let Prototype = "int(float)"; } def SignbitL : Builtin { let Spellings = ["__builtin_signbitl"]; - let Attributes = [FunctionWithBuiltinPrefix, NoThrow, Const, Constexpr]; + let Attributes = [FunctionWithBuiltinPrefix, NoThrow, Const, + Constexpr]; let Prototype = "int(long double)"; } @@ -771,9 +748,8 @@ def Clrsb : Builtin, BitInt_Long_LongLongTemplate { // there exists native types on the target that are 32- and 64-bits wide, unless // these conditions are fulfilled these builtins will operate on a not intended // bitwidth. -def BSwap - : Builtin, - Template<["unsigned short", "uint32_t", "uint64_t"], ["16", "32", "64"]> { +def BSwap : Builtin, Template<["unsigned short", "uint32_t", "uint64_t"], + ["16", "32", "64"]> { let Spellings = ["__builtin_bswap"]; let Attributes = [NoThrow, Const, Constexpr]; let Prototype = "T(T)"; @@ -847,15 +823,13 @@ def BuiltinCalloc : Builtin { def BuiltinConstantP : Builtin { let Spellings = ["__builtin_constant_p"]; - let Attributes = [NoThrow, Const, CustomTypeChecking, UnevaluatedArguments, - Constexpr]; + let Attributes = [NoThrow, Const, CustomTypeChecking, UnevaluatedArguments, Constexpr]; let Prototype = "int(...)"; } def BuiltinClassifyType : Builtin { let Spellings = ["__builtin_classify_type"]; - let Attributes = [NoThrow, Const, CustomTypeChecking, UnevaluatedArguments, - Constexpr]; + let Attributes = [NoThrow, Const, CustomTypeChecking, UnevaluatedArguments, Constexpr]; let Prototype = "int(...)"; } @@ -1159,8 +1133,7 @@ def StpncpyChk : Builtin { def SNPrintfChk : Builtin { let Spellings = ["__builtin___snprintf_chk"]; let Attributes = [FunctionWithBuiltinPrefix, PrintfFormat<4>]; - let Prototype = - "int(char* restrict, size_t, int, size_t, char const* restrict, ...)"; + let Prototype = "int(char* restrict, size_t, int, size_t, char const* restrict, ...)"; } def SPrintfChk : Builtin { @@ -1172,15 +1145,13 @@ def SPrintfChk : Builtin { def VSNPrintfChk : Builtin { let Spellings = ["__builtin___vsnprintf_chk"]; let Attributes = [FunctionWithBuiltinPrefix, VPrintfFormat<4>]; - let Prototype = "int(char* restrict, size_t, int, size_t, char const* " - "restrict, __builtin_va_list)"; + let Prototype = "int(char* restrict, size_t, int, size_t, char const* restrict, __builtin_va_list)"; } def VSPrintfChk : Builtin { let Spellings = ["__builtin___vsprintf_chk"]; let Attributes = [FunctionWithBuiltinPrefix, VPrintfFormat<3>]; - let Prototype = "int(char* restrict, int, size_t, char const* restrict, " - "__builtin_va_list)"; + let Prototype = "int(char* restrict, int, size_t, char const* restrict, __builtin_va_list)"; } def FPrintfChk : Builtin { @@ -1198,8 +1169,7 @@ def PrintfChk : Builtin { def VFPrintfChk : Builtin { let Spellings = ["__builtin___vfprintf_chk"]; let Attributes = [FunctionWithBuiltinPrefix, VPrintfFormat<2>]; - let Prototype = - "int(FILE* restrict, int, char const* restrict, __builtin_va_list)"; + let Prototype = "int(FILE* restrict, int, char const* restrict, __builtin_va_list)"; } def VPrintfChk : Builtin { @@ -2565,8 +2535,7 @@ def SyncFetchAndUMax : Builtin { let Prototype = "unsigned int(unsigned int volatile*, unsigned int)"; } -// ignored glibc builtin, see -// https://sourceware.org/bugzilla/show_bug.cgi?id=25399 +// ignored glibc builtin, see https://sourceware.org/bugzilla/show_bug.cgi?id=25399 def WarnMemsetZeroLen : Builtin { let Spellings = ["__warn_memset_zero_len"]; let Attributes = [NoThrow, Pure]; @@ -2616,10 +2585,9 @@ def BittestAndSet : MSLangBuiltin, MSInt32_64Template { let Prototype = "unsigned char(T*, T)"; } -def MSByteswap - : MSLibBuiltin<"stdlib.h">, - Template<["unsigned short", "msuint32_t", "unsigned long long int"], - ["_ushort", "_ulong", "_uint64"]> { +def MSByteswap : MSLibBuiltin<"stdlib.h">, + Template<["unsigned short", "msuint32_t", "unsigned long long int"], + ["_ushort", "_ulong", "_uint64"]> { let Spellings = ["_byteswap"]; let Attributes = [NoThrow, Const]; let Prototype = "T(T)"; @@ -3230,24 +3198,21 @@ def VPrintf : LibBuiltin<"stdio.h"> { def VfPrintf : LibBuiltin<"stdio.h"> { let Spellings = ["vfprintf"]; let Attributes = [NoThrow, VPrintfFormat<1>, NonNull<NonOptimizing, [0, 1]>]; - let Prototype = - "int(FILE* restrict, char const* restrict, __builtin_va_list)"; + let Prototype = "int(FILE* restrict, char const* restrict, __builtin_va_list)"; let AddBuiltinPrefixedAlias = 1; } def VsnPrintf : LibBuiltin<"stdio.h"> { let Spellings = ["vsnprintf"]; let Attributes = [NoThrow, VPrintfFormat<2>, NonNull<NonOptimizing, [2]>]; - let Prototype = - "int(char* restrict, size_t, char const* restrict, __builtin_va_list)"; + let Prototype = "int(char* restrict, size_t, char const* restrict, __builtin_va_list)"; let AddBuiltinPrefixedAlias = 1; } def VsPrintf : LibBuiltin<"stdio.h"> { let Spellings = ["vsprintf"]; let Attributes = [NoThrow, VPrintfFormat<1>, NonNull<NonOptimizing, [0, 1]>]; - let Prototype = - "int(char* restrict, char const* restrict, __builtin_va_list)"; + let Prototype = "int(char* restrict, char const* restrict, __builtin_va_list)"; let AddBuiltinPrefixedAlias = 1; } @@ -3282,16 +3247,14 @@ def VScanf : LibBuiltin<"stdio.h"> { def VFScanf : LibBuiltin<"stdio.h"> { let Spellings = ["vfscanf"]; let Attributes = [VScanfFormat<1>, NonNull<NonOptimizing, [0, 1]>]; - let Prototype = - "int(FILE* restrict, char const* restrict, __builtin_va_list)"; + let Prototype = "int(FILE* restrict, char const* restrict, __builtin_va_list)"; let AddBuiltinPrefixedAlias = 1; } def VSScanf : LibBuiltin<"stdio.h"> { let Spellings = ["vsscanf"]; let Attributes = [VScanfFormat<1>, NonNull<NonOptimizing, [0, 1]>]; - let Prototype = - "int(char const* restrict, char const* restrict, __builtin_va_list)"; + let Prototype = "int(char const* restrict, char const* restrict, __builtin_va_list)"; let AddBuiltinPrefixedAlias = 1; } @@ -4511,9 +4474,11 @@ def AssumeSeparateStorage : Builtin { // Multiprecision Arithmetic Builtins. -class MPATemplate : Template<["unsigned char", "unsigned short", "unsigned int", - "unsigned long int", "unsigned long long int"], - ["b", "s", "", "l", "ll"]>; +class MPATemplate : Template< + ["unsigned char", "unsigned short", "unsigned int", + "unsigned long int", "unsigned long long int"], + ["b", "s", "", + "l", "ll"]>; def Addc : Builtin, MPATemplate { let Spellings = ["__builtin_addc"]; @@ -4548,9 +4513,9 @@ def MulOverflow : Builtin { let Prototype = "bool(...)"; } -class UOverflowTemplate - : Template<["unsigned int", "unsigned long int", "unsigned long long int"], - ["_overflow", "l_overflow", "ll_overflow"]>; +class UOverflowTemplate : + Template<["unsigned int", "unsigned long int", "unsigned long long int"], + ["_overflow", "l_overflow", "ll_overflow"]>; def UaddOverflow : Builtin, UOverflowTemplate { let Spellings = ["__builtin_uadd"]; @@ -4570,9 +4535,9 @@ def UmulOverflow : Builtin, UOverflowTemplate { let Prototype = "bool(T const, T const, T*)"; } -class SOverflowTemplate - : Template<["int", "long int", "long long int"], ["_overflow", "l_overflow", - "ll_overflow"]>; +class SOverflowTemplate : + Template<["int", "long int", "long long int"], + ["_overflow", "l_overflow", "ll_overflow"]>; def SaddOverflow : Builtin, SOverflowTemplate { let Spellings = ["__builtin_sadd"]; @@ -4832,8 +4797,7 @@ def PtrauthStringDiscriminator : Builtin { // AllocToken builtins. def InferAllocToken : Builtin { let Spellings = ["__builtin_infer_alloc_token"]; - let Attributes = [NoThrow, Const, Pure, CustomTypeChecking, Constexpr, - UnevaluatedArguments]; + let Attributes = [NoThrow, Const, Pure, CustomTypeChecking, Constexpr, UnevaluatedArguments]; let Prototype = "size_t(...)"; } @@ -4936,8 +4900,7 @@ def GetPipeMaxPackets : OCLPipeLangBuiltin { } // OpenCL v2.0 s6.13.17 - Enqueue kernel functions. -// Custom builtin check allows to perform special check of passed block -// arguments. +// Custom builtin check allows to perform special check of passed block arguments. def EnqueueKernel : OCL_DSELangBuiltin { let Spellings = ["enqueue_kernel"]; let Attributes = [CustomTypeChecking, NoThrow]; @@ -5025,7 +4988,7 @@ def GetDeviceSideMangledName : LangBuiltin<"CUDA_LANG"> { } // HLSL -def HLSLAddUint64 : LangBuiltin<"HLSL_LANG"> { +def HLSLAddUint64: LangBuiltin<"HLSL_LANG"> { let Spellings = ["__builtin_hlsl_adduint64"]; let Attributes = [NoThrow, Const]; let Prototype = "void(...)"; @@ -5070,15 +5033,13 @@ def HLSLResourceUninitializedHandle : LangBuiltin<"HLSL_LANG"> { def HLSLResourceHandleFromBinding : LangBuiltin<"HLSL_LANG"> { let Spellings = ["__builtin_hlsl_resource_handlefrombinding"]; let Attributes = [NoThrow]; - let Prototype = "__hlsl_resource_t(__hlsl_resource_t, uint32_t, uint32_t, " - "int32_t, uint32_t, char const*)"; + let Prototype = "__hlsl_resource_t(__hlsl_resource_t, uint32_t, uint32_t, int32_t, uint32_t, char const*)"; } def HLSLResourceHandleFromImplicitBinding : LangBuiltin<"HLSL_LANG"> { let Spellings = ["__builtin_hlsl_resource_handlefromimplicitbinding"]; let Attributes = [NoThrow]; - let Prototype = "__hlsl_resource_t(__hlsl_resource_t, uint32_t, uint32_t, " - "int32_t, uint32_t, char const*)"; + let Prototype = "__hlsl_resource_t(__hlsl_resource_t, uint32_t, uint32_t, int32_t, uint32_t, char const*)"; } def HLSLResourceCounterHandleFromImplicitBinding : LangBuiltin<"HLSL_LANG"> { @@ -5147,12 +5108,6 @@ def HLSLWaveActiveAnyTrue : LangBuiltin<"HLSL_LANG"> { let Prototype = "bool(bool)"; } -def HLSLWaveActiveBitOr : LangBuiltin<"HLSL_LANG"> { - let Spellings = ["__builtin_hlsl_wave_active_bit_or"]; - let Attributes = [NoThrow, Const]; - let Prototype = "unsigned int (unsigned int)"; -} - def HLSLWaveActiveBallot : LangBuiltin<"HLSL_LANG"> { let Spellings = ["__builtin_hlsl_wave_active_ballot"]; let Attributes = [NoThrow, Const]; @@ -5225,18 +5180,16 @@ def HLSLClamp : LangBuiltin<"HLSL_LANG"> { let Prototype = "void(...)"; } -def HLSLCrossFloat : LangBuiltin<"HLSL_LANG"> { +def HLSLCrossFloat: LangBuiltin<"HLSL_LANG"> { let Spellings = ["__builtin_hlsl_crossf32"]; let Attributes = [NoThrow, Const]; - let Prototype = - "_ExtVector<3, float>(_ExtVector<3, float>, _ExtVector<3, float>)"; + let Prototype = "_ExtVector<3, float>(_ExtVector<3, float>, _ExtVector<3, float>)"; } -def HLSLCrossHalf : LangBuiltin<"HLSL_LANG"> { +def HLSLCrossHalf: LangBuiltin<"HLSL_LANG"> { let Spellings = ["__builtin_hlsl_crossf16"]; let Attributes = [NoThrow, Const]; - let Prototype = - "_ExtVector<3, __fp16>(_ExtVector<3, __fp16>, _ExtVector<3, __fp16>)"; + let Prototype = "_ExtVector<3, __fp16>(_ExtVector<3, __fp16>, _ExtVector<3, __fp16>)"; } def HLSLDegrees : LangBuiltin<"HLSL_LANG"> { @@ -5341,7 +5294,7 @@ def HLSLSign : LangBuiltin<"HLSL_LANG"> { let Prototype = "void(...)"; } -def HLSLStep : LangBuiltin<"HLSL_LANG"> { +def HLSLStep: LangBuiltin<"HLSL_LANG"> { let Spellings = ["__builtin_hlsl_step"]; let Attributes = [NoThrow, Const]; let Prototype = "void(...)"; @@ -5359,19 +5312,19 @@ def HLSLBufferUpdateCounter : LangBuiltin<"HLSL_LANG"> { let Prototype = "uint32_t(__hlsl_resource_t, int)"; } -def HLSLSplitDouble : LangBuiltin<"HLSL_LANG"> { +def HLSLSplitDouble: LangBuiltin<"HLSL_LANG"> { let Spellings = ["__builtin_hlsl_elementwise_splitdouble"]; let Attributes = [NoThrow, Const]; let Prototype = "void(...)"; } -def HLSLClip : LangBuiltin<"HLSL_LANG"> { +def HLSLClip: LangBuiltin<"HLSL_LANG"> { let Spellings = ["__builtin_hlsl_elementwise_clip"]; let Attributes = [NoThrow, Const, CustomTypeChecking]; let Prototype = "void(...)"; } -def HLSLGroupMemoryBarrierWithGroupSync : LangBuiltin<"HLSL_LANG"> { +def HLSLGroupMemoryBarrierWithGroupSync: LangBuiltin<"HLSL_LANG"> { let Spellings = ["__builtin_hlsl_group_memory_barrier_with_group_sync"]; let Attributes = [NoThrow, Const]; let Prototype = "void()"; >From 2871282909e5afe5772462476c4df58a4fd4c43b Mon Sep 17 00:00:00 2001 From: KungFuDonkey <[email protected]> Date: Sat, 7 Feb 2026 13:43:16 +0100 Subject: [PATCH 13/13] Cleared failing spv check and added BitOr builtin again --- clang/include/clang/Basic/Builtins.td | 6 ++++++ llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp | 12 ++++++++++-- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/clang/include/clang/Basic/Builtins.td b/clang/include/clang/Basic/Builtins.td index 05e3af4a0e96f..e8777bb7f85ce 100644 --- a/clang/include/clang/Basic/Builtins.td +++ b/clang/include/clang/Basic/Builtins.td @@ -5108,6 +5108,12 @@ def HLSLWaveActiveAnyTrue : LangBuiltin<"HLSL_LANG"> { let Prototype = "bool(bool)"; } +def HLSLWaveActiveBitOr : LangBuiltin<"HLSL_LANG"> { + let Spellings = ["__builtin_hlsl_wave_active_bit_or"]; + let Attributes = [NoThrow, Const]; + let Prototype = "void (...)"; +} + def HLSLWaveActiveBallot : LangBuiltin<"HLSL_LANG"> { let Spellings = ["__builtin_hlsl_wave_active_ballot"]; let Attributes = [NoThrow, Const]; diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp index 1c91c37ffdfd5..6ccdb2b09cde2 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp @@ -2920,6 +2920,15 @@ bool SPIRVInstructionSelector::selectWaveReduce( return true; } +bool SPIRVInstructionSelector::selectWaveReduceOp(Register ResVReg, + const SPIRVType *ResType, + MachineInstr &I, + unsigned Opcode) { + return selectWaveReduceOp( + ResVReg, ResType, I, false, + [&](Register InputRegister, bool IsUnsigned) { return Opcode; }); +} + bool SPIRVInstructionSelector::selectWaveExclusiveScanSum( Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const { return selectWaveExclusiveScan(ResVReg, ResType, I, /*IsUnsigned*/ false, @@ -4055,8 +4064,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, case Intrinsic::spv_wave_is_first_lane: return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformElect); case Intrinsic::spv_wave_reduce_or: - return selectWaveOpInst(ResVReg, ResType, I, - SPIRV::OpGroupNonUniformBitwiseOr); + return selectWaveReduceOp(ResVReg, ResType, I, SPIRV::OpGroupNonUniformBitwiseOr); case Intrinsic::spv_wave_reduce_umax: return selectWaveReduceMax(ResVReg, ResType, I, /*IsUnsigned*/ true); case Intrinsic::spv_wave_reduce_max: _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
