https://github.com/arichardson updated https://github.com/llvm/llvm-project/pull/176870
>From 001723836b4e027afb6c311eac346ad0c9911f69 Mon Sep 17 00:00:00 2001 From: Alex Richardson <[email protected]> Date: Mon, 19 Jan 2026 22:58:07 -0800 Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?= =?UTF-8?q?itial=20version?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Created using spr 1.3.8-beta.1 --- .../Driver/print-supported-extensions-riscv.c | 1 + llvm/lib/Target/RISCV/RISCVFeatures.td | 23 ++++++++++++++++++- llvm/test/CodeGen/RISCV/features-info.ll | 2 ++ llvm/test/MC/RISCV/invalid-attribute.s | 4 ++-- .../TargetParser/RISCVISAInfoTest.cpp | 1 + 5 files changed, 28 insertions(+), 3 deletions(-) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 548a0d5cf6200..9eb2d2e25d01b 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -239,6 +239,7 @@ // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions // CHECK-NEXT: p 0.18 'P' ('Base P' (Packed SIMD)) +// CHECK-NEXT: y 0.96 'Y' ('Base Y' (CHERI)) // CHECK-NEXT: zibi 0.1 'Zibi' (Branch with Immediate) // CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad) // CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index b8d1f775ff322..b818a356d6ce5 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1119,6 +1119,28 @@ def HasStdExtZbkbOrP "'Zbkb' (Bitmanip instructions for Cryptography) or " "'Base P' (Packed-SIMD)">; +// "Y" extension (CHERI support) + +def FeatureStdExtY : RISCVExperimentalExtension<0, 96, "'Base Y' (CHERI)">; +def HasStdExtY + : Predicate<"Subtarget->hasStdExtY()">, + AssemblerPredicate<(all_of FeatureStdExtY), "'Base Y' (CHERI)">; + +// When enabled all memory operations (e.g. loads/stores) uses capability +// registers as the base operand instead of the address sub-register. +// Currently, capability mode needs to be chosen at assembly time, but follow-up +// commits will add support for "hybrid" mode that adds instructions to +// dynamically switch between capability mode and address mode (the latter being +// fully backwards compatible with non-Y code). +def FeatureCapMode : SubtargetFeature<"cap-mode", "IsCapMode", "true", + "Capability pointer mode">; +def IsCapMode + : Predicate<"Subtarget->isCapMode()">, + AssemblerPredicate<(all_of FeatureCapMode), "Capability Pointer Mode">; +def NotCapMode : Predicate<"!Subtarget->isCapMode()">, + AssemblerPredicate<(all_of(not FeatureCapMode)), + "Not Capability Pointer Mode">; + //===----------------------------------------------------------------------===// // Vendor extensions //===----------------------------------------------------------------------===// @@ -1980,4 +2002,3 @@ def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7", def TuneVentanaVeyron : SubtargetFeature<"ventana-veyron", "RISCVProcFamily", "VentanaVeyron", "Ventana Veyron-Series processors">; - diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 1bafca4dff945..6f8b37f3a06d3 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -14,6 +14,7 @@ ; CHECK-NEXT: b - 'B' (the collection of the Zba, Zbb, Zbs extensions). ; CHECK-NEXT: bfext-fusion - Enable SLLI+SRLI (bitfield extract) macrofusion. ; CHECK-NEXT: c - 'C' (Compressed Instructions). +; CHECK-NEXT: cap-mode - Capability pointer mode. ; CHECK-NEXT: conditional-cmv-fusion - Enable branch+c.mv fusion. ; CHECK-NEXT: d - 'D' (Double-Precision Floating-Point). ; CHECK-NEXT: disable-latency-sched-heuristic - Disable latency scheduling heuristic. @@ -34,6 +35,7 @@ ; CHECK-NEXT: experimental-xrivosvizip - 'XRivosVizip' (Rivos Vector Register Zips). ; CHECK-NEXT: experimental-xsfmclic - 'XSfmclic' (SiFive CLIC Machine-mode CSRs). ; CHECK-NEXT: experimental-xsfsclic - 'XSfsclic' (SiFive CLIC Supervisor-mode CSRs). +; CHECK-NEXT: experimental-y - 'Y' ('Base Y' (CHERI)). ; CHECK-NEXT: experimental-zalasr - 'Zalasr' (Load-Acquire and Store-Release Instructions). ; CHECK-NEXT: experimental-zibi - 'Zibi' (Branch with Immediate). ; CHECK-NEXT: experimental-zicfilp - 'Zicfilp' (Landing pad). diff --git a/llvm/test/MC/RISCV/invalid-attribute.s b/llvm/test/MC/RISCV/invalid-attribute.s index c640fccd15ae5..bdc10790157d7 100644 --- a/llvm/test/MC/RISCV/invalid-attribute.s +++ b/llvm/test/MC/RISCV/invalid-attribute.s @@ -13,8 +13,8 @@ .attribute arch, "foo" # CHECK: [[@LINE-1]]:18: error: invalid arch name 'foo', string must begin with rv32{i,e,g}, rv64{i,e,g}, or a supported profile name{{$}} -.attribute arch, "rv32i2p1_y2p0" -# CHECK: [[@LINE-1]]:18: error: invalid arch name 'rv32i2p1_y2p0', invalid standard user-level extension 'y' +.attribute arch, "rv32i2p1_o2p0" +# CHECK: [[@LINE-1]]:18: error: invalid arch name 'rv32i2p1_o2p0', invalid standard user-level extension 'o' .attribute stack_align, "16" # CHECK: [[@LINE-1]]:25: error: expected numeric constant diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 6d078b56ec30a..f77c9d0e7655b 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1392,6 +1392,7 @@ R"(All available -march extensions for RISC-V Experimental extensions p 0.18 + y 0.96 zibi 0.1 zicfilp 1.0 This is a long dummy description zicfiss 1.0 >From fdec2144fe5fa7445091466a08f29664979703ea Mon Sep 17 00:00:00 2001 From: Alex Richardson <[email protected]> Date: Thu, 22 Jan 2026 14:19:23 -0800 Subject: [PATCH 2/3] drop cap-mode Created using spr 1.3.8-beta.1 --- llvm/lib/Target/RISCV/RISCVFeatures.td | 15 --------------- llvm/test/CodeGen/RISCV/features-info.ll | 1 - 2 files changed, 16 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 4763d9fd28229..4e87b2fdb41c1 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1129,21 +1129,6 @@ def FeatureStdExtY : RISCVExperimentalExtension<0, 96, "'Base Y' (CHERI)">; def HasStdExtY : Predicate<"Subtarget->hasStdExtY()">, AssemblerPredicate<(all_of FeatureStdExtY), "'Base Y' (CHERI)">; -// When enabled all memory operations (e.g. loads/stores) uses capability -// registers as the base operand instead of the address sub-register. -// Currently, capability mode needs to be chosen at assembly time, but follow-up -// commits will add support for "hybrid" mode that adds instructions to -// dynamically switch between capability mode and address mode (the latter being -// fully backwards compatible with non-Y code). -def FeatureCapMode : SubtargetFeature<"cap-mode", "IsCapMode", "true", - "Capability pointer mode">; -def IsCapMode : Predicate<"Subtarget->isCapMode()">, - AssemblerPredicate<(all_of FeatureCapMode), - "Capability Pointer Mode">; -def NotCapMode : Predicate<"!Subtarget->isCapMode()">, - AssemblerPredicate<(all_of (not FeatureCapMode)), - "Not Capability Pointer Mode">; - //===----------------------------------------------------------------------===// // Vendor extensions //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 62e3cf2be96c1..71fd3b6ddc543 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -14,7 +14,6 @@ ; CHECK-NEXT: b - 'B' (the collection of the Zba, Zbb, Zbs extensions). ; CHECK-NEXT: bfext-fusion - Enable SLLI+SRLI (bitfield extract) macrofusion. ; CHECK-NEXT: c - 'C' (Compressed Instructions). -; CHECK-NEXT: cap-mode - Capability pointer mode. ; CHECK-NEXT: conditional-cmv-fusion - Enable branch+c.mv fusion. ; CHECK-NEXT: d - 'D' (Double-Precision Floating-Point). ; CHECK-NEXT: disable-latency-sched-heuristic - Disable latency scheduling heuristic. >From 6f69979d82db77b96ab3688071b68b6c23663f7d Mon Sep 17 00:00:00 2001 From: Alex Richardson <[email protected]> Date: Thu, 22 Jan 2026 17:07:47 -0800 Subject: [PATCH 3/3] update one more test Created using spr 1.3.8-beta.1 --- llvm/test/CodeGen/RISCV/attributes.ll | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 6cd41425e715e..aa76811d7982f 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -301,6 +301,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+sdext %s -o - | FileCheck --check-prefix=RV64SDEXT %s ; RUN: llc -mtriple=riscv64 -mattr=+sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-p %s -o - | FileCheck --check-prefix=RV64P %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-y %s -o - | FileCheck --check-prefix=RV64Y %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zibi %s -o - | FileCheck --check-prefix=RV64ZIBI %s @@ -618,6 +619,7 @@ ; RV64SDEXT: .attribute 5, "rv64i2p1_sdext1p0" ; RV64SDTRIG: .attribute 5, "rv64i2p1_sdtrig1p0" ; RV64P: .attribute 5, "rv64i2p1_p0p18" +; RV64Y: .attribute 5, "rv64i2p1_y0p96" ; RV64ZIBI: .attribute 5, "rv64i2p1_zibi0p1" ; RVI20U32: .attribute 5, "rv32i2p1" _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
