================
@@ -1818,7 +1818,51 @@ CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID,
const CallExpr *expr) {
case X86::BI__builtin_ia32_rdrand64_step:
case X86::BI__builtin_ia32_rdseed16_step:
case X86::BI__builtin_ia32_rdseed32_step:
- case X86::BI__builtin_ia32_rdseed64_step:
+ case X86::BI__builtin_ia32_rdseed64_step: {
+ llvm::StringRef intrinsicName;
+ switch (builtinID) {
+ default:
+ llvm_unreachable("Unsupported intrinsic!");
+ case X86::BI__builtin_ia32_rdrand16_step:
+ intrinsicName = "x86.rdrand.16";
+ break;
+ case X86::BI__builtin_ia32_rdrand32_step:
+ intrinsicName = "x86.rdrand.32";
+ break;
+ case X86::BI__builtin_ia32_rdrand64_step:
+ intrinsicName = "x86.rdrand.64";
+ break;
+ case X86::BI__builtin_ia32_rdseed16_step:
+ intrinsicName = "x86.rdseed.16";
+ break;
+ case X86::BI__builtin_ia32_rdseed32_step:
+ intrinsicName = "x86.rdseed.32";
+ break;
+ case X86::BI__builtin_ia32_rdseed64_step:
+ intrinsicName = "x86.rdseed.64";
+ break;
+ }
+
+ mlir::Location loc = getLoc(expr->getExprLoc());
+ mlir::Type randTy = cast<cir::PointerType>(ops[0].getType()).getPointee();
+ llvm::SmallVector<mlir::Type, 2> resultTypes = {randTy,
+ builder.getUInt32Ty()};
+ cir::RecordType resRecord =
+ cir::RecordType::get(&getMLIRContext(), resultTypes, false, false,
+ cir::RecordType::RecordKind::Struct);
+
+ mlir::Value call =
+ emitIntrinsicCallOp(builder, loc, intrinsicName, resRecord);
+ mlir::Value rand =
+ cir::ExtractMemberOp::create(builder, loc, randTy, call, 0);
+ Address addr =
+ Address(ops[0], clang::CharUnits::fromQuantity(
+ builder.getCIRIntOrFloatBitWidth(randTy) / 8));
----------------
fileho wrote:
You are right, the version with just `ops[0]` provides correct alignment in IR.
I overlooked it since it is defined in `cir::CIRBaseBuilderTy` and shadowed by
`CIRGenBuilderTy`
I made changes to test alignment on the level of llvm IR. It is no longer
explicit in CIR IR.
https://github.com/llvm/llvm-project/pull/175439
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