================ @@ -159,6 +159,7 @@ Changes to the RISC-V Backend * DWARF fission is now compatible with linker relaxations, allowing `-gsplit-dwarf` and `-mrelax` to be used together when building for the RISC-V platform. * The Xqci Qualcomm uC Vendor Extension is no longger marked as experimental. +* `-mcpu=spacemit-x100` is now supported. ---------------- lukel97 wrote:
Nit, I think the release notes from the previous release word new processor definitions as: ```suggestion * `-mcpu=spacemit-x100` was added. ``` https://github.com/llvm/llvm-project/pull/173988 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
