[clang] [llvm] [RISCV] Add SpacemiT A100 processor definition (PR #174052)

Sun, 04 Jan 2026 23:40:40 -0800 

================
@@ -735,6 +735,38 @@ def XIANGSHAN_KUNMINGHU : 
RISCVProcessorModel<"xiangshan-kunminghu",
                                                TuneZExtWFusion,
                                                TuneShiftedZExtWFusion]>;
 
+def SPACEMIT_A100 : RISCVProcessorModel<"spacemit-a100",
+                                        SpacemitX60Model,
+                                        !listconcat(
+                                        !listremove(RVA23S64Features,
----------------
zqb-all wrote:

Thanks, addressed. 
Use `RVA23U64Features`  and remove  `FeatureStdExtSmepmp`, 
`FeatureStdExtSmnpm`, `FeatureStdExtSmstateen`, `FeatureStdExtSspm`,

https://github.com/llvm/llvm-project/pull/174052
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