llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-mlir @llvm/pr-subscribers-backend-m68k Author: willmafh (willmafh) <details> <summary>Changes</summary> --- Full diff: https://github.com/llvm/llvm-project/pull/174333.diff 10 Files Affected: - (modified) clang/lib/Format/WhitespaceManager.h (+1-1) - (modified) libcxxabi/src/cxa_personality.cpp (+1-1) - (modified) lldb/test/API/functionalities/gdb_remote_client/TestXMLRegisterFlags.py (+1-1) - (modified) llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (+1-1) - (modified) llvm/lib/Target/AMDGPU/R600ISelLowering.cpp (+1-1) - (modified) llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp (+1-1) - (modified) llvm/tools/llvm-objdump/MachODump.cpp (+1-1) - (modified) llvm/utils/TableGen/Basic/TableGen.cpp (+1-1) - (modified) mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-yaml-gen.cpp (+1-1) - (modified) mlir/tools/mlir-tblgen/OpGenHelpers.h (+1-1) ``````````diff diff --git a/clang/lib/Format/WhitespaceManager.h b/clang/lib/Format/WhitespaceManager.h index 3e6fa9dc32978..64a8f9b4fa857 100644 --- a/clang/lib/Format/WhitespaceManager.h +++ b/clang/lib/Format/WhitespaceManager.h @@ -234,7 +234,7 @@ class WhitespaceManager { /// Align consecutive bitfields over all \c Changes. void alignConsecutiveBitFields(); - /// Align consecutive colon. For bitfields, TableGen DAGArgs and defintions. + /// Align consecutive colon. For bitfields, TableGen DAGArgs and definitions. void alignConsecutiveColons(const FormatStyle::AlignConsecutiveStyle &AlignStyle, TokenType Type); diff --git a/libcxxabi/src/cxa_personality.cpp b/libcxxabi/src/cxa_personality.cpp index 77b2eb53af0e4..81edd41383610 100644 --- a/libcxxabi/src/cxa_personality.cpp +++ b/libcxxabi/src/cxa_personality.cpp @@ -23,7 +23,7 @@ #if __has_feature(ptrauth_calls) -// CXXABI depends on defintions in libunwind as pointer auth couples the +// CXXABI depends on definitions in libunwind as pointer auth couples the // definitions # include "libunwind.h" diff --git a/lldb/test/API/functionalities/gdb_remote_client/TestXMLRegisterFlags.py b/lldb/test/API/functionalities/gdb_remote_client/TestXMLRegisterFlags.py index d7849500c378d..1d0fd00ede3f0 100644 --- a/lldb/test/API/functionalities/gdb_remote_client/TestXMLRegisterFlags.py +++ b/lldb/test/API/functionalities/gdb_remote_client/TestXMLRegisterFlags.py @@ -487,7 +487,7 @@ def test_format_disables_flags(self): @skipIfXmlSupportMissing @skipIfRemote def test_xml_includes(self): - # Certain targets e.g. s390x QEMU split their defintions over multiple + # Certain targets e.g. s390x QEMU split their definitions over multiple # files that are included into target.xml. self.setup_multidoc_test( { diff --git a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp index 5edbc4caf3fae..1c24232095a69 100644 --- a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp +++ b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp @@ -2542,7 +2542,7 @@ MCSection *TargetLoweringObjectFileXCOFF::SelectSectionForGlobal( // For BSS kind, zero initialized data must be emitted to the .data section // because external linkage control sections that get mapped to the .bss - // section will be linked as tentative defintions, which is only appropriate + // section will be linked as tentative definitions, which is only appropriate // for SectionKind::Common. if (Kind.isData() || Kind.isReadOnlyWithRel() || Kind.isBSS()) { if (TM.getDataSections()) { diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp index 3c4f115d7251a..5f6ab5c7ab7ff 100644 --- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp @@ -2191,7 +2191,7 @@ R600TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const { case AtomicRMWInst::UIncWrap: case AtomicRMWInst::UDecWrap: // FIXME: Cayman at least appears to have instructions for this, but the - // instruction defintions appear to be missing. + // instruction definitions appear to be missing. return AtomicExpansionKind::CmpXChg; case AtomicRMWInst::Xchg: { const DataLayout &DL = RMW->getFunction()->getDataLayout(); diff --git a/llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp b/llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp index 9b755e021c5f2..6f650a8c79ff8 100644 --- a/llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp +++ b/llvm/lib/Target/M68k/MCTargetDesc/M68kMCCodeEmitter.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// /// /// \file -/// This file contains defintions for M68k code emitter. +/// This file contains definitions for M68k code emitter. /// //===----------------------------------------------------------------------===// diff --git a/llvm/tools/llvm-objdump/MachODump.cpp b/llvm/tools/llvm-objdump/MachODump.cpp index 44d7c11343f93..e6d2067e8884a 100644 --- a/llvm/tools/llvm-objdump/MachODump.cpp +++ b/llvm/tools/llvm-objdump/MachODump.cpp @@ -3606,7 +3606,7 @@ namespace { // These are structs in the Objective-C meta data and read to produce the // comments for disassembly. While these are part of the ABI they are no -// public defintions. So the are here not in include/llvm/BinaryFormat/MachO.h +// public definitions. So the are here not in include/llvm/BinaryFormat/MachO.h // . // The cfstring object in a 64-bit Mach-O file. diff --git a/llvm/utils/TableGen/Basic/TableGen.cpp b/llvm/utils/TableGen/Basic/TableGen.cpp index a655cbbc16096..402193424ab4f 100644 --- a/llvm/utils/TableGen/Basic/TableGen.cpp +++ b/llvm/utils/TableGen/Basic/TableGen.cpp @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the global defintions (mostly command line parameters) +// This file contains the global definitions (mostly command line parameters) // shared between llvm-tblgen and llvm-min-tblgen. // //===----------------------------------------------------------------------===// diff --git a/mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-yaml-gen.cpp b/mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-yaml-gen.cpp index b8e28c6757b0e..67dbab8ca79f9 100644 --- a/mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-yaml-gen.cpp +++ b/mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-yaml-gen.cpp @@ -505,7 +505,7 @@ static const char bannerFormat[] = R"FMT( // {3}: documentation (summary + description) // {4}: op attribute list // {5}: builder methods taking standalone attribute parameters -// {6}: additional method defintions +// {6}: additional method definitions // {7}: additional methods for attributes used by indexing maps static const char structuredOpOdsHeaderFormat[] = R"FMT( //===----------------------------------------------------------------------===// diff --git a/mlir/tools/mlir-tblgen/OpGenHelpers.h b/mlir/tools/mlir-tblgen/OpGenHelpers.h index 62ae32cacc688..3cd171d10c08a 100644 --- a/mlir/tools/mlir-tblgen/OpGenHelpers.h +++ b/mlir/tools/mlir-tblgen/OpGenHelpers.h @@ -29,7 +29,7 @@ getRequestedOpDefinitions(const llvm::RecordKeeper &records); /// Regenerate using python -c"print(set(sorted(__import__('keyword').kwlist)))" bool isPythonReserved(llvm::StringRef str); -/// Shard the op defintions into the number of shards set by "op-shard-count". +/// Shard the op definitions into the number of shards set by "op-shard-count". void shardOpDefinitions( ArrayRef<const llvm::Record *> defs, SmallVectorImpl<ArrayRef<const llvm::Record *>> &shardedDefs); `````````` </details> https://github.com/llvm/llvm-project/pull/174333 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
