================
@@ -0,0 +1,230 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 6
+
+// RUN: %clang_cc1 -std=hlsl202x -finclude-default-header -x hlsl -triple \
+// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
+// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s
+
+// CHECK-LABEL: define hidden noundef i32
@_Z8Return11u11matrix_typeILm4ELm4EiE(
+// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [16 x i32], align 4
+// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32>
poison, <1 x i32> zeroinitializer
+// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0
+// CHECK-NEXT: ret i32 [[CAST_VTRUNC]]
+//
+int Return11(int4x4 A) {
+ return A._11;
+}
+
+// CHECK-LABEL: define hidden noundef i32
@_Z8Return12u11matrix_typeILm4ELm4EiE(
+// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [16 x i32], align 4
+// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32>
poison, <1 x i32> <i32 1>
+// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0
+// CHECK-NEXT: ret i32 [[CAST_VTRUNC]]
+//
+int Return12(int4x4 A) {
+ return A._12;
+}
+
+// CHECK-LABEL: define hidden noundef i32
@_Z8Return13u11matrix_typeILm4ELm4EiE(
+// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [16 x i32], align 4
+// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32>
poison, <1 x i32> <i32 2>
+// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0
+// CHECK-NEXT: ret i32 [[CAST_VTRUNC]]
+//
+int Return13(int4x4 A) {
+ return A._13;
+}
+
+// CHECK-LABEL: define hidden noundef i32
@_Z8Return14u11matrix_typeILm4ELm4EiE(
+// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [16 x i32], align 4
+// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32>
poison, <1 x i32> <i32 3>
+// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0
+// CHECK-NEXT: ret i32 [[CAST_VTRUNC]]
+//
+int Return14(int4x4 A) {
+ return A._14;
+}
+
+// CHECK-LABEL: define hidden noundef i32
@_Z8Return21u11matrix_typeILm4ELm4EiE(
+// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [16 x i32], align 4
+// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32>
poison, <1 x i32> <i32 4>
+// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0
+// CHECK-NEXT: ret i32 [[CAST_VTRUNC]]
+//
+int Return21(int4x4 A) {
+ return A._21;
+}
+
+// CHECK-LABEL: define hidden noundef i32
@_Z8Return22u11matrix_typeILm4ELm4EiE(
+// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [16 x i32], align 4
+// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32>
poison, <1 x i32> <i32 5>
+// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0
+// CHECK-NEXT: ret i32 [[CAST_VTRUNC]]
+//
+int Return22(int4x4 A) {
+ return A._22;
+}
+
+// CHECK-LABEL: define hidden noundef i32
@_Z8Return23u11matrix_typeILm4ELm4EiE(
+// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [16 x i32], align 4
+// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32>
poison, <1 x i32> <i32 6>
+// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0
+// CHECK-NEXT: ret i32 [[CAST_VTRUNC]]
+//
+int Return23(int4x4 A) {
+ return A._23;
+}
+
+// CHECK-LABEL: define hidden noundef i32
@_Z8Return24u11matrix_typeILm4ELm4EiE(
+// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [16 x i32], align 4
+// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32>
poison, <1 x i32> <i32 7>
+// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0
+// CHECK-NEXT: ret i32 [[CAST_VTRUNC]]
+//
+int Return24(int4x4 A) {
+ return A._24;
+}
+
+// CHECK-LABEL: define hidden noundef i32
@_Z8Return31u11matrix_typeILm4ELm4EiE(
+// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [16 x i32], align 4
+// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32>
poison, <1 x i32> <i32 8>
+// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0
+// CHECK-NEXT: ret i32 [[CAST_VTRUNC]]
+//
+int Return31(int4x4 A) {
+ return A._31;
+}
+
+// CHECK-LABEL: define hidden noundef i32
@_Z8Return32u11matrix_typeILm4ELm4EiE(
+// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [16 x i32], align 4
+// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32>
poison, <1 x i32> <i32 9>
+// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0
+// CHECK-NEXT: ret i32 [[CAST_VTRUNC]]
+//
+int Return32(int4x4 A) {
+ return A._32;
+}
+
+// CHECK-LABEL: define hidden noundef i32
@_Z8Return33u11matrix_typeILm4ELm4EiE(
+// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [16 x i32], align 4
+// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32>
poison, <1 x i32> <i32 10>
+// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0
+// CHECK-NEXT: ret i32 [[CAST_VTRUNC]]
+//
+int Return33(int4x4 A) {
+ return A._33;
+}
+
+// CHECK-LABEL: define hidden noundef i32
@_Z8Return34u11matrix_typeILm4ELm4EiE(
+// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [16 x i32], align 4
+// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32>
poison, <1 x i32> <i32 11>
+// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0
+// CHECK-NEXT: ret i32 [[CAST_VTRUNC]]
+//
+int Return34(int4x4 A) {
+ return A._34;
+}
+
+// CHECK-LABEL: define hidden noundef i32
@_Z8Return41u11matrix_typeILm4ELm4EiE(
+// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [16 x i32], align 4
+// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32>
poison, <1 x i32> <i32 12>
+// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0
+// CHECK-NEXT: ret i32 [[CAST_VTRUNC]]
+//
+int Return41(int4x4 A) {
+ return A._41;
+}
+
+// CHECK-LABEL: define hidden noundef i32
@_Z8Return42u11matrix_typeILm4ELm4EiE(
+// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [16 x i32], align 4
+// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32>
poison, <1 x i32> <i32 13>
+// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0
+// CHECK-NEXT: ret i32 [[CAST_VTRUNC]]
+//
+int Return42(int4x4 A) {
+ return A._42;
+}
+
+// CHECK-LABEL: define hidden noundef i32
@_Z8Return43u11matrix_typeILm4ELm4EiE(
+// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [16 x i32], align 4
+// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32>
poison, <1 x i32> <i32 14>
+// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0
+// CHECK-NEXT: ret i32 [[CAST_VTRUNC]]
+//
+int Return43(int4x4 A) {
+ return A._43;
+}
+
+// CHECK-LABEL: define hidden noundef i32
@_Z8Return44u11matrix_typeILm4ELm4EiE(
+// CHECK-SAME: <16 x i32> noundef [[A:%.*]]) #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: [[A_ADDR:%.*]] = alloca [16 x i32], align 4
+// CHECK-NEXT: store <16 x i32> [[A]], ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP0:%.*]] = load <16 x i32>, ptr [[A_ADDR]], align 4
+// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[TMP0]], <16 x i32>
poison, <1 x i32> <i32 15>
+// CHECK-NEXT: [[CAST_VTRUNC:%.*]] = extractelement <1 x i32> [[TMP1]], i32 0
+// CHECK-NEXT: ret i32 [[CAST_VTRUNC]]
+//
+int Return44(int4x4 A) {
+ return A._44;
+}
+
----------------
hekota wrote:
I am wondering if it is necessary to include every single combination of the
indices in this test. Maybe 2-3 variants would suffice?
https://github.com/llvm/llvm-project/pull/171225
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