================
@@ -1507,6 +1507,15 @@ static uint64_t getTypeSize(mlir::Type type,
mlir::Operation &op) {
return llvm::divideCeil(layout.getTypeSizeInBits(type), 8);
}
+mlir::LogicalResult CIRToLLVMPrefetchOpLowering::matchAndRewrite(
+ cir::PrefetchOp op, OpAdaptor adaptor,
+ mlir::ConversionPatternRewriter &rewriter) const {
+ rewriter.replaceOpWithNewOp<mlir::LLVM::Prefetch>(
+ op, adaptor.getAddr(), adaptor.getIsWrite(), adaptor.getLocality(),
+ /*DataCache*/ 1);
----------------
andykaylor wrote:
```suggestion
/*DataCache=*/1);
```
https://github.com/llvm/llvm-project/pull/164387
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