github-actions[bot] wrote:
<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
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<details>
<summary>
You can test this locally with the following command:
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``````````bash
git-clang-format --diff origin/main HEAD --extensions h,cpp --
clang/lib/Basic/Targets/RISCV.cpp clang/lib/Basic/Targets/RISCV.h
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h --diff_from_common_commit
``````````
:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:
</details>
<details>
<summary>
View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
b/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
index c703d80db..98b636e8e 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
@@ -134,11 +134,9 @@ bool RISCVExpandAtomicPseudo::expandMI(MachineBasicBlock
&MBB,
return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::And, false, 64,
NextMBBI);
case RISCV::PseudoAtomicLoadOr32:
- return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Or, false, 32,
- NextMBBI);
+ return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Or, false, 32,
NextMBBI);
case RISCV::PseudoAtomicLoadOr64:
- return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Or, false, 64,
- NextMBBI);
+ return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Or, false, 64,
NextMBBI);
case RISCV::PseudoAtomicLoadXor32:
return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Xor, false, 32,
NextMBBI);
@@ -153,28 +151,28 @@ bool RISCVExpandAtomicPseudo::expandMI(MachineBasicBlock
&MBB,
NextMBBI);
case RISCV::PseudoAtomicLoadMin32:
return expandAtomicMinMaxOp(MBB, MBBI, AtomicRMWInst::Min, false, 32,
- NextMBBI);
+ NextMBBI);
case RISCV::PseudoAtomicLoadMin64:
return expandAtomicMinMaxOp(MBB, MBBI, AtomicRMWInst::Min, false, 64,
- NextMBBI);
+ NextMBBI);
case RISCV::PseudoAtomicLoadMax32:
return expandAtomicMinMaxOp(MBB, MBBI, AtomicRMWInst::Max, false, 32,
- NextMBBI);
+ NextMBBI);
case RISCV::PseudoAtomicLoadMax64:
return expandAtomicMinMaxOp(MBB, MBBI, AtomicRMWInst::Max, false, 64,
- NextMBBI);
+ NextMBBI);
case RISCV::PseudoAtomicLoadUMin32:
return expandAtomicMinMaxOp(MBB, MBBI, AtomicRMWInst::UMin, false, 32,
- NextMBBI);
+ NextMBBI);
case RISCV::PseudoAtomicLoadUMin64:
return expandAtomicMinMaxOp(MBB, MBBI, AtomicRMWInst::UMin, false, 64,
- NextMBBI);
+ NextMBBI);
case RISCV::PseudoAtomicLoadUMax32:
return expandAtomicMinMaxOp(MBB, MBBI, AtomicRMWInst::UMax, false, 32,
- NextMBBI);
+ NextMBBI);
case RISCV::PseudoAtomicLoadUMax64:
return expandAtomicMinMaxOp(MBB, MBBI, AtomicRMWInst::UMax, false, 64,
- NextMBBI);
+ NextMBBI);
case RISCV::PseudoMaskedAtomicSwap32:
return expandAtomicBinOp(MBB, MBBI, AtomicRMWInst::Xchg, true, 32,
NextMBBI);
@@ -523,14 +521,12 @@ static void insertSext(const RISCVInstrInfo *TII,
DebugLoc DL,
.addReg(ShamtReg);
}
-static void doAtomicMinMaxOpExpansion(const RISCVInstrInfo *TII, MachineInstr
&MI,
- DebugLoc DL, MachineBasicBlock *ThisMBB,
- MachineBasicBlock *LoopHeadMBB,
- MachineBasicBlock *LoopIfBodyMBB,
- MachineBasicBlock *LoopTailMBB,
- MachineBasicBlock *DoneMBB,
- AtomicRMWInst::BinOp BinOp, int Width,
- const RISCVSubtarget *STI) {
+static void doAtomicMinMaxOpExpansion(
+ const RISCVInstrInfo *TII, MachineInstr &MI, DebugLoc DL,
+ MachineBasicBlock *ThisMBB, MachineBasicBlock *LoopHeadMBB,
+ MachineBasicBlock *LoopIfBodyMBB, MachineBasicBlock *LoopTailMBB,
+ MachineBasicBlock *DoneMBB, AtomicRMWInst::BinOp BinOp, int Width,
+ const RISCVSubtarget *STI) {
Register DestReg = MI.getOperand(0).getReg();
Register ScratchReg = MI.getOperand(1).getReg();
Register AddrReg = MI.getOperand(2).getReg();
@@ -587,7 +583,8 @@ static void doAtomicMinMaxOpExpansion(const RISCVInstrInfo
*TII, MachineInstr &M
// .looptail:
// sc.[w|d] scratch, scratch, (addr)
// bnez scratch, loop
- BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width, STI)),
ScratchReg)
+ BuildMI(LoopTailMBB, DL, TII->get(getSCForRMW(Ordering, Width, STI)),
+ ScratchReg)
.addReg(ScratchReg)
.addReg(AddrReg);
BuildMI(LoopTailMBB, DL, TII->get(RISCV::BNE))
@@ -596,14 +593,12 @@ static void doAtomicMinMaxOpExpansion(const
RISCVInstrInfo *TII, MachineInstr &M
.addMBB(LoopHeadMBB);
}
-static void doMaskedAtomicMinMaxOpExpansion(const RISCVInstrInfo *TII,
MachineInstr &MI,
- DebugLoc DL, MachineBasicBlock
*ThisMBB,
- MachineBasicBlock *LoopHeadMBB,
- MachineBasicBlock *LoopIfBodyMBB,
- MachineBasicBlock *LoopTailMBB,
- MachineBasicBlock *DoneMBB,
- AtomicRMWInst::BinOp BinOp, int
Width,
- const RISCVSubtarget *STI) {
+static void doMaskedAtomicMinMaxOpExpansion(
+ const RISCVInstrInfo *TII, MachineInstr &MI, DebugLoc DL,
+ MachineBasicBlock *ThisMBB, MachineBasicBlock *LoopHeadMBB,
+ MachineBasicBlock *LoopIfBodyMBB, MachineBasicBlock *LoopTailMBB,
+ MachineBasicBlock *DoneMBB, AtomicRMWInst::BinOp BinOp, int Width,
+ const RISCVSubtarget *STI) {
assert(Width == 32 && "Should never need to expand masked 64-bit
operations");
Register DestReg = MI.getOperand(0).getReg();
Register Scratch1Reg = MI.getOperand(1).getReg();
``````````
</details>
https://github.com/llvm/llvm-project/pull/163672
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