rez5427 wrote:
> > Machine CSE is before this register coalescer, Machine CSE will see
> > something like:
> > ```
> > li a2, 42
> > a0 = copy a2
> > ```
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> > So Machine CSE will not eliminate this pattern.
>
> IIRC, MachineCSE will try copy propagation. Looks failing in this case. Maybe
> we should find out why it fails.
I checked MachineCSE.cpp there is a comment on the top:
```
// This pass performs global common subexpression elimination on machine
// instructions using a scoped hash table based value numbering scheme. It
// must be run while the machine function is still in SSA form.
```
This requirement is essential because SSA form guarantees that each virtual
register is defined exactly once and never overwritten.
Without this property, the pass could not safely determine whether two
instructions compute the same value.
Consider the following pseudo-MachineIR:
```
bb.0:
$x10 = ADDI $x0, 42
%0 = COPY $x10
$x10 = ADDI $x0, 100
%1 = ADD %0, $x0
```
If the machine function were not in SSA form, the pass could not know that $x10
was redefined between %0 and %1.
And in the function PerformTrivialCopyPropagation it skip the phisical register
by `!SrcReg.isVirtual()`
```
bool MachineCSEImpl::PerformTrivialCopyPropagation(MachineInstr *MI,
MachineBasicBlock *MBB) {
bool Changed = false;
for (MachineOperand &MO : MI->all_uses()) {
Register Reg = MO.getReg();
if (!Reg.isVirtual())
continue;
bool OnlyOneUse = MRI->hasOneNonDBGUse(Reg);
MachineInstr *DefMI = MRI->getVRegDef(Reg);
if (!DefMI || !DefMI->isCopy())
continue;
Register SrcReg = DefMI->getOperand(1).getReg();
if (!SrcReg.isVirtual())
continue;
```
https://github.com/llvm/llvm-project/pull/163047
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