================
@@ -24483,6 +24483,26 @@ ISD::NodeType 
RISCVTargetLowering::getExtendForAtomicCmpSwapArg() const {
   return Subtarget.hasStdExtZacas() ? ISD::ANY_EXTEND : ISD::SIGN_EXTEND;
 }
 
+ISD::NodeType RISCVTargetLowering::getExtendForAtomicRMWArg(unsigned Op) const 
{
+  // Zaamo will use amo<op>.w which does not require extension.
+  if (Subtarget.hasStdExtZaamo() || Subtarget.hasForcedAtomics())
+    return ISD::ANY_EXTEND;
+
+  // Zalasr pseudo expansions with comparison
+  assert(Subtarget.hasStdExtZalrsc());
+  switch (Op) {
+  case ISD::ATOMIC_LOAD_MIN:
+  case ISD::ATOMIC_LOAD_MAX:
+    return ISD::SIGN_EXTEND;
+  case ISD::ATOMIC_LOAD_UMIN:
+  case ISD::ATOMIC_LOAD_UMAX:
+    return ISD::ZERO_EXTEND;
----------------
slachowsky wrote:

Good idea.

The LR.W used in the ExpandAtomicPseudos is always sign-extending the value 
read from memory, so the idea is to shrink the sequence from:

```
atomicrmw_umax_i32_monotonic:           # @atomicrmw_umax_i32_monotonic
# %bb.0:
        slli    a1, a1, 32
        srli    a2, a1, 32
.LBB0_1:                                # =>This Inner Loop Header: Depth=1
        lr.w    a1, (a0)
        slli    a3, a1, 32
        srli    a3, a3, 32
        bgeu    a3, a2, .LBB0_3
# %bb.2:                                #   in Loop: Header=BB0_1 Depth=1
        mv      a3, a2
.LBB0_3:                                #   in Loop: Header=BB0_1 Depth=1
        sc.w    a3, a3, (a0)
        bnez    a3, .LBB0_1
# %bb.4:
        mv      a0, a1
        ret
 ```
 
To something like:

``` 
atomicrmw_umax_i32_monotonic:           # @atomicrmw_umax_i32_monotonic
# %bb.0:
        sext.w a2, a1
.LBB0_1:                                # =>This Inner Loop Header: Depth=1
        lr.w    a1, (a0)
        bgeu    a3, a2, .LBB0_3
# %bb.2:                                #   in Loop: Header=BB0_1 Depth=1
        mv      a3, a2
.LBB0_3:                                #   in Loop: Header=BB0_1 Depth=1
        sc.w    a3, a3, (a0)
        bnez    a3, .LBB0_1
# %bb.4:
        mv      a0, a1
        ret
``` 



https://github.com/llvm/llvm-project/pull/163672
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