================
@@ -1877,8 +1880,9 @@ struct AdditionalKeywords {
// In Verilog the colon in a default label is optional.
return Tok.is(TT_CaseLabelColon) ||
(Tok.is(tok::kw_default) &&
- !(Next && Next->isOneOf(tok::colon, tok::semi, kw_clocking, kw_iff,
- kw_input, kw_output, kw_sequence)));
+ (!Next ||
+ Next->isNotOneOf(tok::colon, tok::semi, kw_clocking, kw_iff,
+ kw_input, kw_output, kw_sequence)));
----------------
HazardyKnusperkeks wrote:
I like the `!` to be more in the inner parenthesis, and `!A || B` reads also
nice as that is the canonical representation of the implication. If `Next`
exists, it is not one of ...
https://github.com/llvm/llvm-project/pull/161021
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