llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: Georgiy Samoylov (sga-sc) <details> <summary>Changes</summary> This patch enables support for debug entry values. This improves quality of debug info for RISC-V --- Full diff: https://github.com/llvm/llvm-project/pull/157703.diff 4 Files Affected: - (modified) clang/lib/Frontend/CompilerInvocation.cpp (+4-3) - (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+6-6) - (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+3) - (added) llvm/test/DebugInfo/RISCV/dw_op_entry_value.ll (+74) ``````````diff diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp index 8411d00cc7812..23e7d6d989930 100644 --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -1975,9 +1975,10 @@ bool CompilerInvocation::ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, } const llvm::Triple::ArchType DebugEntryValueArchs[] = { - llvm::Triple::x86, llvm::Triple::x86_64, llvm::Triple::aarch64, - llvm::Triple::arm, llvm::Triple::armeb, llvm::Triple::mips, - llvm::Triple::mipsel, llvm::Triple::mips64, llvm::Triple::mips64el}; + llvm::Triple::x86, llvm::Triple::x86_64, llvm::Triple::aarch64, + llvm::Triple::arm, llvm::Triple::armeb, llvm::Triple::mips, + llvm::Triple::mipsel, llvm::Triple::mips64, llvm::Triple::mips64el, + llvm::Triple::riscv32, llvm::Triple::riscv64}; if (Opts.OptimizationLevel > 0 && Opts.hasReducedDebugInfo() && llvm::is_contained(DebugEntryValueArchs, T.getArch())) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 46f544c0d4df5..3a7e276e03226 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -23257,6 +23257,10 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI, if (VA.isRegLoc()) { // Queue up the argument copies and emit them at the end. RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); + + const TargetOptions &Options = DAG.getTarget().Options; + if (Options.EmitCallSiteInfo) + CSInfo.ArgRegPairs.emplace_back(VA.getLocReg(), i); } else { assert(VA.isMemLoc() && "Argument not register or memory"); assert(!IsTailCall && "Tail call not allowed if stack is used " @@ -23358,9 +23362,7 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI, if (CLI.CFIType) Ret.getNode()->setCFIType(CLI.CFIType->getZExtValue()); DAG.addNoMergeSiteInfo(Ret.getNode(), CLI.NoMerge); - if (MF.getTarget().Options.EmitCallGraphSection && CB && - CB->isIndirectCall()) - DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo)); + DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo)); return Ret; } @@ -23369,10 +23371,8 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI, if (CLI.CFIType) Chain.getNode()->setCFIType(CLI.CFIType->getZExtValue()); - if (MF.getTarget().Options.EmitCallGraphSection && CB && CB->isIndirectCall()) - DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo)); - DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge); + DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo)); Glue = Chain.getValue(1); // Mark the end of the call, which is glued to the call itself. diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index 460bb33f2553a..b6a2f3f79f34f 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -195,6 +195,9 @@ RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT, setMachineOutliner(true); setSupportsDefaultOutlining(true); + // RISC-V supports the debug entry values. + setSupportsDebugEntryValues(true); + if (TT.isOSFuchsia() && !TT.isArch64Bit()) report_fatal_error("Fuchsia is only supported for 64-bit"); diff --git a/llvm/test/DebugInfo/RISCV/dw_op_entry_value.ll b/llvm/test/DebugInfo/RISCV/dw_op_entry_value.ll new file mode 100644 index 0000000000000..bfee2939cba33 --- /dev/null +++ b/llvm/test/DebugInfo/RISCV/dw_op_entry_value.ll @@ -0,0 +1,74 @@ +;; Test RISC-V 64 bit: +; RUN: llc -emit-call-site-info -stop-after=livedebugvalues -mtriple=riscv64-linux-gnu -o - %s | FileCheck %s --check-prefix=CHECK64 +; RUN: llc -force-instr-ref-livedebugvalues=1 -emit-call-site-info -stop-after=livedebugvalues -mtriple=riscv64-linux-gnu -o - %s | FileCheck %s --check-prefix=CHECK64 + +;; Built from source: +;; extern long fn1(long,long,long); +;; long fn2(long a, long b, long c) { +;; long local = fn1(a+b, c, b+10); +;; if (local > 10) +;; return local + 10; +;; return b; +;; } +;; Using command: +;; clang -g -O2 -target riscv64-linux-gnu m.c -c -S -emit-llvm +;; Confirm that info from callSites attribute is used as entry_value in DIExpression. + +;; Test riscv64: +; CHECK64: renamable $x10 = nsw ADD $x11, killed renamable $x10 +; CHECK64-NEXT: DBG_VALUE $x10, $noreg, !{{.*}}, !DIExpression(DW_OP_LLVM_entry_value, 1) + +; ModuleID = 'm.c' +source_filename = "m.c" +target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" +target triple = "riscv64-unknown-linux-gnu" + +; Function Attrs: nounwind uwtable +define dso_local i64 @fn2(i64 noundef %a, i64 noundef %b, i64 noundef %c) local_unnamed_addr #0 !dbg !14 { +entry: + #dbg_value(i64 %a, !19, !DIExpression(), !23) + #dbg_value(i64 %b, !20, !DIExpression(), !23) + #dbg_value(i64 %c, !21, !DIExpression(), !23) + %add = add nsw i64 %b, %a, !dbg !24 + %add1 = add nsw i64 %b, 10, !dbg !25 + %call = tail call i64 @fn1(i64 noundef %add, i64 noundef %c, i64 noundef %add1) #2, !dbg !26 + #dbg_value(i64 %call, !22, !DIExpression(), !23) + %cmp = icmp sgt i64 %call, 10, !dbg !27 + %add2 = add nuw nsw i64 %call, 10, !dbg !27 + %retval.0 = select i1 %cmp, i64 %add2, i64 %b, !dbg !27 + ret i64 %retval.0, !dbg !29 +} + +declare !dbg !30 i64 @fn1(i64 noundef, i64 noundef, i64 noundef) local_unnamed_addr #1 + +attributes #0 = { nounwind uwtable "target-cpu"="generic-rv64" "target-features"="+64bit,+c,+m,+relax,+zicsr,+zmmul" } +attributes #1 = { "target-cpu"="generic-rv64" "target-features"="+64bit,+c,+m,+relax,+zicsr,+zmmul" } +attributes #2 = { nounwind } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3, !4} +!llvm.ident = !{!5} + +!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "m.c", directory: ".") +!2 = !{i32 7, !"Dwarf Version", i32 5} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !{i32 1, !"wchar_size", i32 4} +!5 = !{!"clang"} +!14 = distinct !DISubprogram(name: "fn2", scope: !1, file: !1, line: 2, type: !15, scopeLine: 2, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !18) +!15 = !DISubroutineType(types: !16) +!16 = !{!17, !17, !17, !17} +!17 = !DIBasicType(name: "long", size: 64, encoding: DW_ATE_signed) +!18 = !{!19, !20, !21, !22} +!19 = !DILocalVariable(name: "a", arg: 1, scope: !14, file: !1, line: 2, type: !17) +!20 = !DILocalVariable(name: "b", arg: 2, scope: !14, file: !1, line: 2, type: !17) +!21 = !DILocalVariable(name: "c", arg: 3, scope: !14, file: !1, line: 2, type: !17) +!22 = !DILocalVariable(name: "local", scope: !14, file: !1, line: 3, type: !17) +!23 = !DILocation(line: 0, scope: !14) +!24 = !DILocation(line: 3, column: 21, scope: !14) +!25 = !DILocation(line: 3, column: 29, scope: !14) +!26 = !DILocation(line: 3, column: 16, scope: !14) +!27 = !DILocation(line: 4, column: 13, scope: !28) +!28 = distinct !DILexicalBlock(scope: !14, file: !1, line: 4, column: 7) +!29 = !DILocation(line: 7, column: 1, scope: !14) +!30 = !DISubprogram(name: "fn1", scope: !1, file: !1, line: 1, type: !15, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) `````````` </details> https://github.com/llvm/llvm-project/pull/157703 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
