[clang] [llvm] [RISCV] Support ZVqdot Codegen and C intrinsics (PR #154915)

[Craig Topper via cfe-commits]

================
@@ -52,10 +52,72 @@ let Predicates = [HasStdExtZvqdotq], mayLoad = 0, mayStore 
= 0,
   defm PseudoVQDOT : VPseudoVQDOT_VV_VX;
   defm PseudoVQDOTU : VPseudoVQDOT_VV_VX;
   defm PseudoVQDOTSU : VPseudoVQDOT_VV_VX;
+  // VQDOTUS does not have a VV variant
+  foreach m = MxListVF4 in {
+    defm "PseudoVQDOTUS_VX" : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, 
GPR, m>;
+  }
 }
 
 defvar AllE32Vectors = [VI32MF2, VI32M1, VI32M2, VI32M4, VI32M8];
 defm : VPatBinaryVL_VV_VX<riscv_vqdot_vl, "PseudoVQDOT", AllE32Vectors>;
 defm : VPatBinaryVL_VV_VX<riscv_vqdotu_vl, "PseudoVQDOTU", AllE32Vectors>;
 defm : VPatBinaryVL_VV_VX<riscv_vqdotsu_vl, "PseudoVQDOTSU", AllE32Vectors>;
 
+// These VPat definitions are for vqdot because they have a different operand
+// order with other ternary instructions (i.e. vop.vx vd, vs2, rs1)
+multiclass VPatTernaryV_VX_AAXASwapped<string intrinsic, string instruction,
+                                       list<VTypeInfoToWide> info_pairs> {
+  foreach pair = info_pairs in {
+    defvar VdInfo = pair.Wti;
+    defvar Vs2Info = pair.Vti;
+    let Predicates = GetVTypePredicates<VdInfo>.Predicates in
+    // we have op1 and op2 swapped here
+    defm : VPatTernaryWithPolicy<intrinsic, instruction,
+                                 "V"#VdInfo.ScalarSuffix,
+                                 VdInfo.Vector, Vs2Info.Vector, Vs2Info.Scalar,
+                                 VdInfo.Mask, VdInfo.Log2SEW, VdInfo.LMul,
+                                 VdInfo.RegClass, Vs2Info.RegClass,
+                                 Vs2Info.ScalarRegClass>;
+  }
+}
+
+multiclass VPatTernaryV_VV_AAXASwapped<string intrinsic, string instruction,
+                                       list<VTypeInfoToWide> info_pairs> {
+  foreach pair = info_pairs in {
+    defvar VdInfo = pair.Wti;
+    defvar Vs2Info = pair.Vti;
+    let Predicates = GetVTypePredicates<VdInfo>.Predicates in
+    // we have op1 and op2 swapped here
+    defm : VPatTernaryWithPolicy<intrinsic, instruction,
+                                 "VV",
+                                 VdInfo.Vector, Vs2Info.Vector, Vs2Info.Vector,
+                                 VdInfo.Mask, VdInfo.Log2SEW, VdInfo.LMul,
+                                 VdInfo.RegClass, Vs2Info.RegClass,
+                                 Vs2Info.RegClass>;
+  }
+}
+
+multiclass VPatTernaryV_VV_VX_AAXASwapped<string intrinsic, string instruction,
+                                          list<VTypeInfoToWide> info_pairs>
+    // keep the original VV because the order doesn't matter
----------------
topperc wrote:

What does this comment refer to?

https://github.com/llvm/llvm-project/pull/154915
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