Author: 林克 Date: 2025-08-18T18:03:17+08:00 New Revision: 6842cc556222659256b32883bb2b63ff019100e0
URL: https://github.com/llvm/llvm-project/commit/6842cc556222659256b32883bb2b63ff019100e0 DIFF: https://github.com/llvm/llvm-project/commit/6842cc556222659256b32883bb2b63ff019100e0.diff LOG: [RISCV] Add SpacemiT XSMTVDot (SpacemiT Vector Dot Product) extension. (#151706) The full spec can be found at spacemit-x60 processor support scope: Section 2.1.2.2 (Features): https://developer.spacemit.com/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb#2.1 This patch only supports assembler. Added: llvm/lib/Target/RISCV/RISCVInstrInfoXSpacemiT.td llvm/test/MC/RISCV/xsmtvdot-invalid.s llvm/test/MC/RISCV/xsmtvdot-valid.s Modified: clang/test/Driver/print-supported-extensions-riscv.c clang/test/Driver/riscv-cpus.c llvm/docs/RISCVUsage.rst llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp llvm/lib/Target/RISCV/RISCVFeatures.td llvm/lib/Target/RISCV/RISCVInstrInfo.td llvm/lib/Target/RISCV/RISCVProcessors.td llvm/test/CodeGen/RISCV/features-info.ll llvm/unittests/TargetParser/RISCVISAInfoTest.cpp Removed: ################################################################################ diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 87bbd95877b25..f1a1359b5f555 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -194,6 +194,7 @@ // CHECK-NEXT: xsfvqmaccqoq 1.0 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4)) // CHECK-NEXT: xsifivecdiscarddlone 1.0 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction) // CHECK-NEXT: xsifivecflushdlone 1.0 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction) +// CHECK-NEXT: xsmtvdot 1.0 'XSMTVDot' (SpacemiT Vector Dot Product Extension) // CHECK-NEXT: xtheadba 1.0 'XTHeadBa' (T-Head address calculation instructions) // CHECK-NEXT: xtheadbb 1.0 'XTHeadBb' (T-Head basic bit-manipulation instructions) // CHECK-NEXT: xtheadbs 1.0 'XTHeadBs' (T-Head single-bit instructions) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 2a9c4e7021feb..ea0821cc39c45 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -157,6 +157,7 @@ // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svinval" // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svnapot" // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svpbmt" +// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+xsmtvdot" // MCPU-SPACEMIT-X60-SAME: "-target-abi" "lp64d" // We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string. diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index a29e06cdf838d..f9f3e39727a5a 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -531,6 +531,10 @@ The current vendor extensions supported are: ``XAndesVDot`` LLVM implements `version 5.0.0 of the Andes Vector Dot Product Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification. +``XSMTVDot`` + SpacemiT defines `Intrinsic Matrix Extension (IME) specification <https://github.com/space-mit/riscv-ime-extension-spec/releases/tag/v0429>`__. + LLVM implement the hardware-adapted subset for SpacemiT X60, defined in the `feature document <https://developer.spacemit.com/documentation?token=BWbGwbx7liGW21kq9lucSA6Vnpb#2.1>`__ by SpacemiT. All instructions are prefixed with `smt.` as described in the implementation guide. Note that this implemented subset is `version 1.0.0 of the SpacemiT Vector Dot Product Extension specification`, which is strictly a subset of the full IME specification to reflect the capabilities of SpacemiT X60 hardware correctly. + Experimental C Intrinsics ========================= diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index e0ac59141695f..78be55b3a51d3 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -672,6 +672,8 @@ static constexpr FeatureBitset XAndesGroup = { RISCV::FeatureVendorXAndesVSIntLoad, RISCV::FeatureVendorXAndesVPackFPH, RISCV::FeatureVendorXAndesVDot}; +static constexpr FeatureBitset XSMTGroup = {RISCV::FeatureVendorXSMTVDot}; + static constexpr DecoderListEntry DecoderList32[]{ // Vendor Extensions {DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"}, @@ -692,6 +694,7 @@ static constexpr DecoderListEntry DecoderList32[]{ {RISCV::FeatureVendorXMIPSCBOP}, "MIPS mips.pref"}, {DecoderTableXAndes32, XAndesGroup, "Andes extensions"}, + {DecoderTableXSMT32, XSMTGroup, "SpacemiT extensions"}, // Standard Extensions {DecoderTable32, {}, "standard 32-bit instructions"}, {DecoderTableRV32Only32, {}, "RV32-only standard 32-bit instructions"}, diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index ac0234dd9a5f5..d4ac3c60e2d4c 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1642,6 +1642,14 @@ def HasVendorXAndesVDot AssemblerPredicate<(all_of FeatureVendorXAndesVDot), "'XAndesVDot' (Andes Vector Dot Product Extension)">; +def FeatureVendorXSMTVDot + : RISCVExtension<1, 0, "SpacemiT Vector Dot Product Extension", + [FeatureStdExtZve32f]>; +def HasVendorXSMTVDot + : Predicate<"Subtarget->hasVendorXSMTVDot()">, + AssemblerPredicate<(all_of FeatureVendorXSMTVDot), + "'XSMTVDot' (SpacemiT Vector Dot Product Extension)">; + //===----------------------------------------------------------------------===// // LLVM specific features and extensions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 2a34a24a6ae20..8cbdf0ec7fa33 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -2381,6 +2381,7 @@ include "RISCVInstrInfoXqccmp.td" include "RISCVInstrInfoXMips.td" include "RISCVInstrInfoXRivos.td" include "RISCVInstrInfoXAndes.td" +include "RISCVInstrInfoXSpacemiT.td" //===----------------------------------------------------------------------===// // Global ISel diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSpacemiT.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSpacemiT.td new file mode 100644 index 0000000000000..980931ea12a4f --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSpacemiT.td @@ -0,0 +1,139 @@ +//===-- RISCVInstrInfoXSpacemiT.td -------------------------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the vendor extensions defined by SpacemiT. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Operand definitions. +//===----------------------------------------------------------------------===// + +class SMTVDotOpcode<bits<7> val> { + bits<7> Value = val; +} + +class SMTVEncoding2<bits<2> val> { + bits<2> Value = val; +} + +def OPMMA : SMTVDotOpcode<0b1110001>; +def OPMMA_SLIDE : SMTVDotOpcode<0b1110011>; + +//===----------------------------------------------------------------------===// +// Vector Dot-Product Sign Encoding +// Defines the signed/unsigned mixing modes for vector dot-product operations. +// Encoding format: [1:0] bits +// 00: UU (Unsigned x Unsigned) +// 01: US (Unsigned x Signed) +// 10: SU (Signed x Unsigned) +// 11: SS (Signed x Signed) +//===----------------------------------------------------------------------===// +def SMT_VDot_UU : SMTVEncoding2<0b00>; +def SMT_VDot_US : SMTVEncoding2<0b01>; +def SMT_VDot_SU : SMTVEncoding2<0b10>; +def SMT_VDot_SS : SMTVEncoding2<0b11>; + +//===----------------------------------------------------------------------===// +// Vector Dot-Product Sliding Window Modes +// Encoding format: [1:0] bits +// 00: Slide1 (1-element sliding stride) +// 01: Slide2 (2-element sliding stride) +// 10: Slide3 (3-element sliding stride) +// 11: Reserved +// +// Used in sliding-window dot-product operations: +// vd = vs1 • vs2.slide{1|2|3} // • = dot product +//===----------------------------------------------------------------------===// +def SMT_VDot_Slide1 : SMTVEncoding2<0b00>; +def SMT_VDot_Slide2 : SMTVEncoding2<0b01>; +def SMT_VDot_Slide3 : SMTVEncoding2<0b10>; + +//===----------------------------------------------------------------------===// +// Instruction formats +//===----------------------------------------------------------------------===// + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { +// Base vector dot product (no slide) format. +class RVInstSMTVDot<SMTVEncoding2 sign, string opcodestr, string argstr> + : RVInst<(outs VRM2:$vd), (ins VR:$vs1, VR:$vs2), opcodestr, argstr, [], InstFormatR> { + bits<5> vd; + bits<5> vs1; + bits<5> vs2; + + let Inst{31-25} = OPMMA.Value; + let Inst{24-20} = vs2; + let Inst{19-15} = vs1; + let Inst{14} = 0b0; + let Inst{13-12} = sign.Value; + let Inst{11-8} = vd{4-1}; + let Inst{7} = 0b0; + let Inst{6-0} = OPC_CUSTOM_1.Value; +} + +// Sliding-window vector dot product format. +class RVInstSMTVDotSlide<SMTVEncoding2 funct2, SMTVEncoding2 sign, string opcodestr, string argstr> + : RVInst<(outs VRM2:$vd), (ins VRM2:$vs1, VR:$vs2), opcodestr, argstr, [], InstFormatR> { + bits<5> vd; + bits<5> vs1; + bits<5> vs2; + + let Inst{31-25} = OPMMA_SLIDE.Value; + let Inst{24-20} = vs2; + let Inst{19-16} = vs1{4-1}; + let Inst{15-14} = funct2.Value; + let Inst{13-12} = sign.Value; + let Inst{11-8} = vd{4-1}; + let Inst{7} = 0b0; + let Inst{6-0} = OPC_CUSTOM_1.Value; +} +} + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +let DecoderNamespace = "XSMT" in { + +let Predicates = [HasVendorXSMTVDot], ElementsDependOn = EltDepsVL in { +// Base vector dot product (no slide) instructions +// NOTE: Destination registers (vd) MUST be even-numbered (v0, v2, ..., v30) +// due to hardware alignment constraints. Using odd registers may cause undefined behavior. +def VMADOT : RVInstSMTVDot<SMT_VDot_SS, "smt.vmadot", "$vd, $vs1, $vs2">; +def VMADOTU : RVInstSMTVDot<SMT_VDot_UU, "smt.vmadotu", "$vd, $vs1, $vs2">; +def VMADOTSU : RVInstSMTVDot<SMT_VDot_SU, "smt.vmadotsu", "$vd, $vs1, $vs2">; +def VMADOTUS : RVInstSMTVDot<SMT_VDot_US, "smt.vmadotus", "$vd, $vs1, $vs2">; + +//===----------------------------------------------------------------------===// +// Sliding-window Vector Dot Product Instructions +// +// The numeric suffix (1, 2, 3) specifies the stride of the sliding window: +// 1: Window slides by 1 element per operation +// 2: Window slides by 2 elements per operation +// 3: Window slides by 3 elements per operation +// +// These instructions compute dot products with overlapping operand windows +// where the window position increments by <N> elements between computations. +//===----------------------------------------------------------------------===// +// NOTE: Destination registers (vd) and first source register (vs1) MUST be +// even-numbered (v0, v2, ..., v30) due to hardware alignment constraints. +// Using odd registers may cause undefined behavior. +def VMADOT1 : RVInstSMTVDotSlide<SMT_VDot_Slide1, SMT_VDot_SS, "smt.vmadot1", "$vd, $vs1, $vs2">; +def VMADOT1U : RVInstSMTVDotSlide<SMT_VDot_Slide1, SMT_VDot_UU, "smt.vmadot1u", "$vd, $vs1, $vs2">; +def VMADOT1SU : RVInstSMTVDotSlide<SMT_VDot_Slide1, SMT_VDot_SU, "smt.vmadot1su", "$vd, $vs1, $vs2">; +def VMADOT1US : RVInstSMTVDotSlide<SMT_VDot_Slide1, SMT_VDot_US, "smt.vmadot1us", "$vd, $vs1, $vs2">; +def VMADOT2 : RVInstSMTVDotSlide<SMT_VDot_Slide2, SMT_VDot_SS, "smt.vmadot2", "$vd, $vs1, $vs2">; +def VMADOT2U : RVInstSMTVDotSlide<SMT_VDot_Slide2, SMT_VDot_UU, "smt.vmadot2u", "$vd, $vs1, $vs2">; +def VMADOT2SU : RVInstSMTVDotSlide<SMT_VDot_Slide2, SMT_VDot_SU, "smt.vmadot2su", "$vd, $vs1, $vs2">; +def VMADOT2US : RVInstSMTVDotSlide<SMT_VDot_Slide2, SMT_VDot_US, "smt.vmadot2us", "$vd, $vs1, $vs2">; +def VMADOT3 : RVInstSMTVDotSlide<SMT_VDot_Slide3, SMT_VDot_SS, "smt.vmadot3", "$vd, $vs1, $vs2">; +def VMADOT3U : RVInstSMTVDotSlide<SMT_VDot_Slide3, SMT_VDot_UU, "smt.vmadot3u", "$vd, $vs1, $vs2">; +def VMADOT3SU : RVInstSMTVDotSlide<SMT_VDot_Slide3, SMT_VDot_SU, "smt.vmadot3su", "$vd, $vs1, $vs2">; +def VMADOT3US : RVInstSMTVDotSlide<SMT_VDot_Slide3, SMT_VDot_US, "smt.vmadot3us", "$vd, $vs1, $vs2">; +} +} \ No newline at end of file diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 31d2b3a10db53..f89d94f41b69f 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -673,6 +673,7 @@ def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60", FeatureStdExtZvfh, FeatureStdExtZvkt, FeatureStdExtZvl256b, + FeatureVendorXSMTVDot, FeatureUnalignedScalarMem]), [TuneDLenFactor2, TuneOptimizedNF2SegmentLoadStore, diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 60b94adcc4c79..f966f800589b7 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -217,6 +217,7 @@ ; CHECK-NEXT: xsfvqmaccqoq - 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4)). ; CHECK-NEXT: xsifivecdiscarddlone - 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction). ; CHECK-NEXT: xsifivecflushdlone - 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction). +; CHECK-NEXT: xsmtvdot - 'XSMTVDot' (SpacemiT Vector Dot Product Extension). ; CHECK-NEXT: xtheadba - 'XTHeadBa' (T-Head address calculation instructions). ; CHECK-NEXT: xtheadbb - 'XTHeadBb' (T-Head basic bit-manipulation instructions). ; CHECK-NEXT: xtheadbs - 'XTHeadBs' (T-Head single-bit instructions). diff --git a/llvm/test/MC/RISCV/xsmtvdot-invalid.s b/llvm/test/MC/RISCV/xsmtvdot-invalid.s new file mode 100644 index 0000000000000..9dce654ecc7f5 --- /dev/null +++ b/llvm/test/MC/RISCV/xsmtvdot-invalid.s @@ -0,0 +1,52 @@ +# RUN: not llvm-mc -triple riscv32 -mattr=+xsmtvdot < %s 2>&1 \ +# RUN: | FileCheck %s +# RUN: not llvm-mc -triple riscv64 -mattr=+xsmtvdot < %s 2>&1 \ +# RUN: | FileCheck %s + +# NoSlide +smt.vmadot v1, v2, v2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction +smt.vmadotu v1, v2, v2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction +smt.vmadotsu v1, v2, v2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction +smt.vmadotus v1, v2, v2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction + +# Slide = 1 +smt.vmadot1 v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction +smt.vmadot1u v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction +smt.vmadot1su v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction +smt.vmadot1us v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction +smt.vmadot1 v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction +smt.vmadot1u v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction +smt.vmadot1su v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction +smt.vmadot1us v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction +smt.vmadot1 v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction +smt.vmadot1u v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction +smt.vmadot1su v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction +smt.vmadot1us v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction + +# Slide = 2 +smt.vmadot2 v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction +smt.vmadot2u v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction +smt.vmadot2su v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction +smt.vmadot2us v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction +smt.vmadot2 v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction +smt.vmadot2u v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction +smt.vmadot2su v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction +smt.vmadot2us v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction +smt.vmadot2 v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction +smt.vmadot2u v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction +smt.vmadot2su v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction +smt.vmadot2us v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction + +# Slide = 3 +smt.vmadot3 v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction +smt.vmadot3u v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction +smt.vmadot3su v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction +smt.vmadot3us v1, v2, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction +smt.vmadot3 v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction +smt.vmadot3u v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction +smt.vmadot3su v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction +smt.vmadot3us v2, v1, v2 # CHECK: :[[@LINE]]:19: error: invalid operand for instruction +smt.vmadot3 v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction +smt.vmadot3u v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction +smt.vmadot3su v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction +smt.vmadot3us v1, v3, v2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction \ No newline at end of file diff --git a/llvm/test/MC/RISCV/xsmtvdot-valid.s b/llvm/test/MC/RISCV/xsmtvdot-valid.s new file mode 100644 index 0000000000000..9e66419b10e16 --- /dev/null +++ b/llvm/test/MC/RISCV/xsmtvdot-valid.s @@ -0,0 +1,114 @@ +# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+xsmtvdot %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xsmtvdot %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+xsmtvdot %s \ +# RUN: | llvm-objdump -d --mattr=+xsmtvdot - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xsmtvdot %s \ +# RUN: | llvm-objdump -d --mattr=+xsmtvdot - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+xsmtvdot %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xsmtvdot %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +# CHECK-INST: smt.vmadot v16, v0, v8 +# CHECK-ENCODING: [0x2b,0x38,0x80,0xe2] +# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +# CHECK-UNKNOWN: e280382b <unknown> +smt.vmadot v16, v0, v8 + +# CHECK-INST: smt.vmadotu v18, v1, v9 +# CHECK-ENCODING: [0x2b,0x89,0x90,0xe2] +# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +# CHECK-UNKNOWN: e290892b <unknown> +smt.vmadotu v18, v1, v9 + +# CHECK-INST: smt.vmadotsu v20, v2, v10 +# CHECK-ENCODING: [0x2b,0x2a,0xa1,0xe2] +# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +# CHECK-UNKNOWN: e2a12a2b <unknown> +smt.vmadotsu v20, v2, v10 + +# CHECK-INST: smt.vmadotus v22, v3, v11 +# CHECK-ENCODING: [0x2b,0x9b,0xb1,0xe2] +# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +# CHECK-UNKNOWN: e2b19b2b <unknown> +smt.vmadotus v22, v3, v11 + +# CHECK-INST: smt.vmadot1 v24, v16, v12 +# CHECK-ENCODING: [0x2b,0x3c,0xc8,0xe6] +# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +# CHECK-UNKNOWN: e6c83c2b <unknown> +smt.vmadot1 v24, v16, v12 + +# CHECK-INST: smt.vmadot1u v26, v18, v13 +# CHECK-ENCODING: [0x2b,0x0d,0xd9,0xe6] +# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +# CHECK-UNKNOWN: e6d90d2b <unknown> +smt.vmadot1u v26, v18, v13 + +# CHECK-INST: smt.vmadot1su v28, v20, v14 +# CHECK-ENCODING: [0x2b,0x2e,0xea,0xe6] +# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +# CHECK-UNKNOWN: e6ea2e2b <unknown> +smt.vmadot1su v28, v20, v14 + +# CHECK-INST: smt.vmadot1us v30, v22, v15 +# CHECK-ENCODING: [0x2b,0x1f,0xfb,0xe6] +# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +# CHECK-UNKNOWN: e6fb1f2b <unknown> +smt.vmadot1us v30, v22, v15 + +# CHECK-INST: smt.vmadot2 v0, v24, v4 +# CHECK-ENCODING: [0x2b,0x70,0x4c,0xe6] +# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +# CHECK-UNKNOWN: e64c702b <unknown> +smt.vmadot2 v0, v24, v4 + +# CHECK-INST: smt.vmadot2u v2, v26, v5 +# CHECK-ENCODING: [0x2b,0x41,0x5d,0xe6] +# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +# CHECK-UNKNOWN: e65d412b <unknown> +smt.vmadot2u v2, v26, v5 + +# CHECK-INST: smt.vmadot2su v4, v28, v6 +# CHECK-ENCODING: [0x2b,0x62,0x6e,0xe6] +# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +# CHECK-UNKNOWN: e66e622b <unknown> +smt.vmadot2su v4, v28, v6 + +# CHECK-INST: smt.vmadot2us v6, v30, v7 +# CHECK-ENCODING: [0x2b,0x53,0x7f,0xe6] +# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +# CHECK-UNKNOWN: e67f532b <unknown> +smt.vmadot2us v6, v30, v7 + +# CHECK-INST: smt.vmadot3 v8, v0, v8 +# CHECK-ENCODING: [0x2b,0xb4,0x80,0xe6] +# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +# CHECK-UNKNOWN: e680b42b <unknown> +smt.vmadot3 v8, v0, v8 + +# CHECK-INST: smt.vmadot3u v10, v2, v9 +# CHECK-ENCODING: [0x2b,0x85,0x91,0xe6] +# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +# CHECK-UNKNOWN: e691852b <unknown> +smt.vmadot3u v10, v2, v9 + +# CHECK-INST: smt.vmadot3su v12, v4, v10 +# CHECK-ENCODING: [0x2b,0xa6,0xa2,0xe6] +# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +# CHECK-UNKNOWN: e6a2a62b <unknown> +smt.vmadot3su v12, v4, v10 + +# CHECK-INST: smt.vmadot3us v14, v6, v11 +# CHECK-ENCODING: [0x2b,0x97,0xb3,0xe6] +# CHECK-ERROR: instruction requires the following: 'XSMTVDot' (SpacemiT Vector Dot Product Extension){{$}} +# CHECK-UNKNOWN: e6b3972b <unknown> +smt.vmadot3us v14, v6, v11 \ No newline at end of file diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index db58d95d2d82c..ff0af566b05b7 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1165,6 +1165,7 @@ R"(All available -march extensions for RISC-V xsfvqmaccqoq 1.0 xsifivecdiscarddlone 1.0 xsifivecflushdlone 1.0 + xsmtvdot 1.0 xtheadba 1.0 xtheadbb 1.0 xtheadbs 1.0 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
