Author: Nikita Popov Date: 2025-08-18T09:23:48+02:00 New Revision: 246a64a12e576a1ff51b6712b9926a7320384275
URL: https://github.com/llvm/llvm-project/commit/246a64a12e576a1ff51b6712b9926a7320384275 DIFF: https://github.com/llvm/llvm-project/commit/246a64a12e576a1ff51b6712b9926a7320384275.diff LOG: [Clang] Rename HasLegalHalfType -> HasFastHalfType (NFC) (#153163) This option is confusingly named. What it actually controls is whether, under the default of `-ffloat16-excess-precision=standard`, it is beneficial for performance to perform calculations on float (without intermediate rounding) or not. For `-ffloat16-excess-precision=none` the LLVM `half` type will always be used, and all backends are expected to legalize it correctly. Added: Modified: clang/include/clang/Basic/TargetInfo.h clang/lib/AST/Type.cpp clang/lib/Basic/TargetInfo.cpp clang/lib/Basic/Targets/AArch64.cpp clang/lib/Basic/Targets/AMDGPU.cpp clang/lib/Basic/Targets/ARM.cpp clang/lib/Basic/Targets/DirectX.h clang/lib/Basic/Targets/Hexagon.cpp clang/lib/Basic/Targets/NVPTX.cpp clang/lib/Basic/Targets/RISCV.cpp clang/lib/Basic/Targets/SPIR.h clang/lib/Basic/Targets/SystemZ.h clang/lib/Basic/Targets/X86.cpp clang/lib/CodeGen/TargetBuiltins/ARM.cpp clang/lib/CodeGen/Targets/ARM.cpp Removed: ################################################################################ diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h index ce4677e540226..25b68622656fa 100644 --- a/clang/include/clang/Basic/TargetInfo.h +++ b/clang/include/clang/Basic/TargetInfo.h @@ -233,8 +233,9 @@ class TargetInfo : public TransferrableTargetInfo, bool TLSSupported; bool VLASupported; bool NoAsmVariants; // True if {|} are normal characters. - bool HasLegalHalfType; // True if the backend supports operations on the half - // LLVM IR type. + bool HasFastHalfType; // True if the backend has native half float support, + // and performing calculations in float instead does + // not have a performance advantage. bool HalfArgsAndReturns; // OpenCL 6.1.1.1, NEON (IEEE 754-2008 half) type. bool HasFloat128; bool HasFloat16; @@ -700,8 +701,9 @@ class TargetInfo : public TransferrableTargetInfo, return 128; } - /// Determine whether _Float16 is supported on this target. - virtual bool hasLegalHalfType() const { return HasLegalHalfType; } + /// Determine whether the target has fast native support for operations + /// on half types. + virtual bool hasFastHalfType() const { return HasFastHalfType; } /// Whether half args and returns are supported. virtual bool allowHalfArgsAndReturns() const { return HalfArgsAndReturns; } diff --git a/clang/lib/AST/Type.cpp b/clang/lib/AST/Type.cpp index f7949e94d227e..5fbf1999ed725 100644 --- a/clang/lib/AST/Type.cpp +++ b/clang/lib/AST/Type.cpp @@ -1627,7 +1627,7 @@ bool QualType::UseExcessPrecision(const ASTContext &Ctx) { switch (BT->getKind()) { case BuiltinType::Kind::Float16: { const TargetInfo &TI = Ctx.getTargetInfo(); - if (TI.hasFloat16Type() && !TI.hasLegalHalfType() && + if (TI.hasFloat16Type() && !TI.hasFastHalfType() && Ctx.getLangOpts().getFloat16ExcessPrecision() != Ctx.getLangOpts().ExcessPrecisionKind::FPP_None) return true; diff --git a/clang/lib/Basic/TargetInfo.cpp b/clang/lib/Basic/TargetInfo.cpp index 21fc084d19772..2fbf1ee39b789 100644 --- a/clang/lib/Basic/TargetInfo.cpp +++ b/clang/lib/Basic/TargetInfo.cpp @@ -62,7 +62,7 @@ TargetInfo::TargetInfo(const llvm::Triple &T) : Triple(T) { TLSSupported = true; VLASupported = true; NoAsmVariants = false; - HasLegalHalfType = false; + HasFastHalfType = false; HalfArgsAndReturns = false; HasFloat128 = false; HasIbm128 = false; diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp index 2b023e5fdb7d8..9e03a0846ffba 100644 --- a/clang/lib/Basic/Targets/AArch64.cpp +++ b/clang/lib/Basic/Targets/AArch64.cpp @@ -142,7 +142,7 @@ AArch64TargetInfo::AArch64TargetInfo(const llvm::Triple &Triple, AddrSpaceMap = &ARM64AddrSpaceMap; // All AArch64 implementations support ARMv8 FP, which makes half a legal type. - HasLegalHalfType = true; + HasFastHalfType = true; HalfArgsAndReturns = true; HasFloat16 = true; HasStrictFP = true; diff --git a/clang/lib/Basic/Targets/AMDGPU.cpp b/clang/lib/Basic/Targets/AMDGPU.cpp index 52cbdbc3719d3..639e735202f26 100644 --- a/clang/lib/Basic/Targets/AMDGPU.cpp +++ b/clang/lib/Basic/Targets/AMDGPU.cpp @@ -251,7 +251,7 @@ AMDGPUTargetInfo::AMDGPUTargetInfo(const llvm::Triple &Triple, BFloat16Format = &llvm::APFloat::BFloat(); } - HasLegalHalfType = true; + HasFastHalfType = true; HasFloat16 = true; WavefrontSize = (GPUFeatures & llvm::AMDGPU::FEATURE_WAVE32) ? 32 : 64; diff --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp index 75fdf38e2104f..3de17d2c829f1 100644 --- a/clang/lib/Basic/Targets/ARM.cpp +++ b/clang/lib/Basic/Targets/ARM.cpp @@ -585,13 +585,13 @@ bool ARMTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, } else if (Feature == "+fp16") { HW_FP |= HW_FP_HP; } else if (Feature == "+fullfp16") { - HasLegalHalfType = true; + HasFastHalfType = true; } else if (Feature == "+dotprod") { DotProd = true; } else if (Feature == "+mve") { MVE |= MVE_INT; } else if (Feature == "+mve.fp") { - HasLegalHalfType = true; + HasFastHalfType = true; FPU |= FPARMV8; MVE |= MVE_INT | MVE_FP; HW_FP |= HW_FP_SP | HW_FP_HP; @@ -1014,11 +1014,11 @@ void ARMTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__ARM_FP_FAST", "1"); // Armv8.2-A FP16 vector intrinsic - if ((FPU & NeonFPU) && HasLegalHalfType) + if ((FPU & NeonFPU) && HasFastHalfType) Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1"); // Armv8.2-A FP16 scalar intrinsics - if (HasLegalHalfType) + if (HasFastHalfType) Builder.defineMacro("__ARM_FEATURE_FP16_SCALAR_ARITHMETIC", "1"); // Armv8.2-A dot product intrinsics diff --git a/clang/lib/Basic/Targets/DirectX.h b/clang/lib/Basic/Targets/DirectX.h index 17240cf358902..bd13c9ee0fd05 100644 --- a/clang/lib/Basic/Targets/DirectX.h +++ b/clang/lib/Basic/Targets/DirectX.h @@ -59,7 +59,7 @@ class LLVM_LIBRARY_VISIBILITY DirectXTargetInfo : public TargetInfo { VLASupported = false; AddrSpaceMap = &DirectXAddrSpaceMap; UseAddrSpaceMapMangling = true; - HasLegalHalfType = true; + HasFastHalfType = true; HasFloat16 = true; NoAsmVariants = true; PlatformMinVersion = Triple.getOSVersion(); diff --git a/clang/lib/Basic/Targets/Hexagon.cpp b/clang/lib/Basic/Targets/Hexagon.cpp index 06dcac03baa5b..cea64f9860036 100644 --- a/clang/lib/Basic/Targets/Hexagon.cpp +++ b/clang/lib/Basic/Targets/Hexagon.cpp @@ -149,7 +149,7 @@ bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasAudio = true; } if (CPU.compare("hexagonv68") >= 0) { - HasLegalHalfType = true; + HasFastHalfType = true; HasFloat16 = true; } return true; diff --git a/clang/lib/Basic/Targets/NVPTX.cpp b/clang/lib/Basic/Targets/NVPTX.cpp index 79995ccc21b27..5cf2dc187b836 100644 --- a/clang/lib/Basic/Targets/NVPTX.cpp +++ b/clang/lib/Basic/Targets/NVPTX.cpp @@ -65,7 +65,7 @@ NVPTXTargetInfo::NVPTXTargetInfo(const llvm::Triple &Triple, GPU = OffloadArch::UNUSED; // PTX supports f16 as a fundamental type. - HasLegalHalfType = true; + HasFastHalfType = true; HasFloat16 = true; if (TargetPointerWidth == 32) diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp index a6a5ec4b325bc..04da4e637af51 100644 --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -427,7 +427,7 @@ bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, ABI = ISAInfo->computeDefaultABI().str(); if (ISAInfo->hasExtension("zfh") || ISAInfo->hasExtension("zhinx")) - HasLegalHalfType = true; + HasFastHalfType = true; FastScalarUnalignedAccess = llvm::is_contained(Features, "+unaligned-scalar-mem"); diff --git a/clang/lib/Basic/Targets/SPIR.h b/clang/lib/Basic/Targets/SPIR.h index 9d0ced2afdbc7..fb15b77065543 100644 --- a/clang/lib/Basic/Targets/SPIR.h +++ b/clang/lib/Basic/Targets/SPIR.h @@ -106,7 +106,7 @@ class LLVM_LIBRARY_VISIBILITY BaseSPIRTargetInfo : public TargetInfo { LongWidth = LongAlign = 64; AddrSpaceMap = &SPIRDefIsPrivMap; UseAddrSpaceMapMangling = true; - HasLegalHalfType = true; + HasFastHalfType = true; HasFloat16 = true; // Define available target features // These must be defined in sorted order! @@ -427,7 +427,7 @@ class LLVM_LIBRARY_VISIBILITY SPIRV64AMDGCNTargetInfo final BFloat16Width = BFloat16Align = 16; BFloat16Format = &llvm::APFloat::BFloat(); - HasLegalHalfType = true; + HasFastHalfType = true; HasFloat16 = true; HalfArgsAndReturns = true; diff --git a/clang/lib/Basic/Targets/SystemZ.h b/clang/lib/Basic/Targets/SystemZ.h index 7f7dcf815bd8f..dc2185e1b45ca 100644 --- a/clang/lib/Basic/Targets/SystemZ.h +++ b/clang/lib/Basic/Targets/SystemZ.h @@ -104,7 +104,7 @@ class LLVM_LIBRARY_VISIBILITY SystemZTargetInfo : public TargetInfo { // -ffloat16-excess-precision=none is given, no conversions will be made // and instead the backend will promote each half operation to float // individually. - HasLegalHalfType = false; + HasFastHalfType = false; HasStrictFP = true; } diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp index 24ecec24d2a4a..dc6f65540e2f9 100644 --- a/clang/lib/Basic/Targets/X86.cpp +++ b/clang/lib/Basic/Targets/X86.cpp @@ -348,7 +348,7 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasAVX512BF16 = true; } else if (Feature == "+avx512fp16") { HasAVX512FP16 = true; - HasLegalHalfType = true; + HasFastHalfType = true; } else if (Feature == "+avx512dq") { HasAVX512DQ = true; } else if (Feature == "+avx512bitalg") { diff --git a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp index 980f7eb714bbf..60413e7b18e85 100644 --- a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp +++ b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp @@ -358,7 +358,7 @@ static Value *emitCallMaybeConstrainedFPBuiltin(CodeGenFunction &CGF, static llvm::FixedVectorType *GetNeonType(CodeGenFunction *CGF, NeonTypeFlags TypeFlags, - bool HasLegalHalfType = true, + bool HasFastHalfType = true, bool V1Ty = false, bool AllowBFloatArgsAndRet = true) { int IsQuad = TypeFlags.isQuad(); @@ -376,7 +376,7 @@ static llvm::FixedVectorType *GetNeonType(CodeGenFunction *CGF, else return llvm::FixedVectorType::get(CGF->Int16Ty, V1Ty ? 1 : (4 << IsQuad)); case NeonTypeFlags::Float16: - if (HasLegalHalfType) + if (HasFastHalfType) return llvm::FixedVectorType::get(CGF->HalfTy, V1Ty ? 1 : (4 << IsQuad)); else return llvm::FixedVectorType::get(CGF->Int16Ty, V1Ty ? 1 : (4 << IsQuad)); @@ -1754,12 +1754,12 @@ Value *CodeGenFunction::EmitCommonNeonBuiltinExpr( const bool Usgn = Type.isUnsigned(); const bool Quad = Type.isQuad(); const bool Floating = Type.isFloatingPoint(); - const bool HasLegalHalfType = getTarget().hasLegalHalfType(); + const bool HasFastHalfType = getTarget().hasFastHalfType(); const bool AllowBFloatArgsAndRet = getTargetHooks().getABIInfo().allowBFloatArgsAndRet(); llvm::FixedVectorType *VTy = - GetNeonType(this, Type, HasLegalHalfType, false, AllowBFloatArgsAndRet); + GetNeonType(this, Type, HasFastHalfType, false, AllowBFloatArgsAndRet); llvm::Type *Ty = VTy; if (!Ty) return nullptr; @@ -1886,7 +1886,7 @@ Value *CodeGenFunction::EmitCommonNeonBuiltinExpr( case NEON::BI__builtin_neon_vcvtq_f32_v: Ops[0] = Builder.CreateBitCast(Ops[0], Ty); Ty = GetNeonType(this, NeonTypeFlags(NeonTypeFlags::Float32, false, Quad), - HasLegalHalfType); + HasFastHalfType); return Usgn ? Builder.CreateUIToFP(Ops[0], Ty, "vcvt") : Builder.CreateSIToFP(Ops[0], Ty, "vcvt"); case NEON::BI__builtin_neon_vcvt_f16_s16: @@ -1895,7 +1895,7 @@ Value *CodeGenFunction::EmitCommonNeonBuiltinExpr( case NEON::BI__builtin_neon_vcvtq_f16_u16: Ops[0] = Builder.CreateBitCast(Ops[0], Ty); Ty = GetNeonType(this, NeonTypeFlags(NeonTypeFlags::Float16, false, Quad), - HasLegalHalfType); + HasFastHalfType); return Usgn ? Builder.CreateUIToFP(Ops[0], Ty, "vcvt") : Builder.CreateSIToFP(Ops[0], Ty, "vcvt"); case NEON::BI__builtin_neon_vcvt_n_f16_s16: @@ -3211,7 +3211,7 @@ Value *CodeGenFunction::EmitARMBuiltinExpr(unsigned BuiltinID, bool rightShift = false; llvm::FixedVectorType *VTy = - GetNeonType(this, Type, getTarget().hasLegalHalfType(), false, + GetNeonType(this, Type, getTarget().hasFastHalfType(), false, getTarget().hasBFloat16Type()); llvm::Type *Ty = VTy; if (!Ty) diff --git a/clang/lib/CodeGen/Targets/ARM.cpp b/clang/lib/CodeGen/Targets/ARM.cpp index 532ba4cead244..3739e16788c3e 100644 --- a/clang/lib/CodeGen/Targets/ARM.cpp +++ b/clang/lib/CodeGen/Targets/ARM.cpp @@ -316,7 +316,7 @@ ABIArgInfo ARMABIInfo::classifyHomogeneousAggregate(QualType Ty, // Base can be a floating-point or a vector. if (const VectorType *VT = Base->getAs<VectorType>()) { // FP16 vectors should be converted to integer vectors - if (!getTarget().hasLegalHalfType() && containsAnyFP16Vectors(Ty)) { + if (!getTarget().hasFastHalfType() && containsAnyFP16Vectors(Ty)) { uint64_t Size = getContext().getTypeSize(VT); auto *NewVecTy = llvm::FixedVectorType::get( llvm::Type::getInt32Ty(getVMContext()), Size / 32); @@ -582,7 +582,7 @@ ABIArgInfo ARMABIInfo::classifyReturnType(QualType RetTy, bool isVariadic, getDataLayout().getAllocaAddrSpace()); // TODO: FP16/BF16 vectors should be converted to integer vectors // This check is similar to isIllegalVectorType - refactor? - if ((!getTarget().hasLegalHalfType() && + if ((!getTarget().hasFastHalfType() && (VT->getElementType()->isFloat16Type() || VT->getElementType()->isHalfType())) || (IsFloatABISoftFP && @@ -679,9 +679,9 @@ bool ARMABIInfo::isIllegalVectorType(QualType Ty) const { // into float, and we don't want the ABI to depend on whether or not they // are supported in hardware. Thus return false to coerce vectors of these // types into integer vectors. - // We do not depend on hasLegalHalfType for bfloat as it is a + // We do not depend on hasFastHalfType for bfloat as it is a // separate IR type. - if ((!getTarget().hasLegalHalfType() && + if ((!getTarget().hasFastHalfType() && (VT->getElementType()->isFloat16Type() || VT->getElementType()->isHalfType())) || (IsFloatABISoftFP && _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
