Author: Craig Topper Date: 2025-07-14T20:52:46-07:00 New Revision: 9a9db2a39c7640ebd803741e4f058598bca04f0b
URL: https://github.com/llvm/llvm-project/commit/9a9db2a39c7640ebd803741e4f058598bca04f0b DIFF: https://github.com/llvm/llvm-project/commit/9a9db2a39c7640ebd803741e4f058598bca04f0b.diff LOG: [RISCV] Prefix mcpu/mtune/march/mabi with '-' in comments. NFC (#148723) Added: Modified: clang/test/Driver/riscv-cpus.c Removed: ################################################################################ diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index d32d1c1a8183f..2698612f815d3 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -287,7 +287,7 @@ // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=xiangshan-nanhu | FileCheck -check-prefix=MTUNE-XIANGSHAN-NANHU %s // MTUNE-XIANGSHAN-NANHU: "-tune-cpu" "xiangshan-nanhu" -// Check mtune alias CPU has resolved to the right CPU according XLEN. +// Check -mtune alias CPU has resolved to the right CPU according XLEN. // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck -check-prefix=MTUNE-GENERIC-32 %s // MTUNE-GENERIC-32: "-tune-cpu" "generic" @@ -304,21 +304,21 @@ // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=native | FileCheck -check-prefix=MTUNE-NATIVE %s // MTUNE-NATIVE-NOT: "-tune-cpu" "native" -// mcpu with default march +// -mcpu with default -march // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e20 | FileCheck -check-prefix=MCPU-SIFIVE-E20 %s // MCPU-SIFIVE-E20: "-nostdsysteminc" "-target-cpu" "sifive-e20" // MCPU-SIFIVE-E20: "-target-feature" "+m" "-target-feature" "+c" // MCPU-SIFIVE-E20: "-target-feature" "+zicsr" "-target-feature" "+zifencei" // MCPU-SIFIVE-E20: "-target-abi" "ilp32" -// mcpu with default march +// -mcpu with default -march // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e21 | FileCheck -check-prefix=MCPU-SIFIVE-E21 %s // MCPU-SIFIVE-E21: "-nostdsysteminc" "-target-cpu" "sifive-e21" // MCPU-SIFIVE-E21: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+c" // MCPU-SIFIVE-E21: "-target-feature" "+zicsr" "-target-feature" "+zifencei" // MCPU-SIFIVE-E21: "-target-abi" "ilp32" -// mcpu with default march +// -mcpu with default -march // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e24 | FileCheck -check-prefix=MCPU-SIFIVE-E24 %s // MCPU-SIFIVE-E24: "-nostdsysteminc" "-target-cpu" "sifive-e24" // MCPU-SIFIVE-E24: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" @@ -326,7 +326,7 @@ // MCPU-SIFIVE-E24: "-target-feature" "+zicsr" "-target-feature" "+zifencei" // MCPU-SIFIVE-E24: "-target-abi" "ilp32f" -// mcpu with default march +// -mcpu with default -march // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e34 | FileCheck -check-prefix=MCPU-SIFIVE-E34 %s // MCPU-SIFIVE-E34: "-nostdsysteminc" "-target-cpu" "sifive-e34" // MCPU-SIFIVE-E34: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" @@ -334,7 +334,7 @@ // MCPU-SIFIVE-E34: "-target-feature" "+zicsr" "-target-feature" "+zifencei" // MCPU-SIFIVE-E34: "-target-abi" "ilp32f" -// mcpu with mabi option +// -mcpu with -mabi option // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s21 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S21 %s // MCPU-ABI-SIFIVE-S21: "-nostdsysteminc" "-target-cpu" "sifive-s21" // MCPU-ABI-SIFIVE-S21: "-target-feature" "+m" "-target-feature" "+a" @@ -342,7 +342,7 @@ // MCPU-ABI-SIFIVE-S21: "-target-feature" "+zicsr" "-target-feature" "+zifencei" // MCPU-ABI-SIFIVE-S21: "-target-abi" "lp64" -// mcpu with mabi option +// -mcpu with -mabi option // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s51 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S51 %s // MCPU-ABI-SIFIVE-S51: "-nostdsysteminc" "-target-cpu" "sifive-s51" // MCPU-ABI-SIFIVE-S51: "-target-feature" "+m" "-target-feature" "+a" @@ -350,7 +350,7 @@ // MCPU-ABI-SIFIVE-S51: "-target-feature" "+zicsr" "-target-feature" "+zifencei" // MCPU-ABI-SIFIVE-S51: "-target-abi" "lp64" -// mcpu with default march +// -mcpu with default -march // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s54 | FileCheck -check-prefix=MCPU-SIFIVE-S54 %s // MCPU-SIFIVE-S54: "-nostdsysteminc" "-target-cpu" "sifive-s54" // MCPU-SIFIVE-S54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" @@ -358,7 +358,7 @@ // MCPU-SIFIVE-S54: "-target-feature" "+zicsr" "-target-feature" "+zifencei" // MCPU-SIFIVE-S54: "-target-abi" "lp64d" -// mcpu with mabi option +// -mcpu with -mabi option // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s76 | FileCheck -check-prefix=MCPU-SIFIVE-S76 %s // MCPU-SIFIVE-S76: "-nostdsysteminc" "-target-cpu" "sifive-s76" // MCPU-SIFIVE-S76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" @@ -366,7 +366,7 @@ // MCPU-SIFIVE-S76: "-target-feature" "+zicsr" "-target-feature" "+zifencei" "-target-feature" "+zihintpause" // MCPU-SIFIVE-S76: "-target-abi" "lp64d" -// mcpu with default march +// -mcpu with default -march // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck -check-prefix=MCPU-SIFIVE-U54 %s // MCPU-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54" // MCPU-SIFIVE-U54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" @@ -374,7 +374,7 @@ // MCPU-SIFIVE-U54: "-target-feature" "+zicsr" "-target-feature" "+zifencei" // MCPU-SIFIVE-U54: "-target-abi" "lp64d" -// mcpu with mabi option +// -mcpu with -mabi option // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-U54 %s // MCPU-ABI-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54" // MCPU-ABI-SIFIVE-U54: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" @@ -382,7 +382,7 @@ // MCPU-ABI-SIFIVE-U54: "-target-feature" "+zicsr" "-target-feature" "+zifencei" // MCPU-ABI-SIFIVE-U54: "-target-abi" "lp64" -// mcpu with default march +// -mcpu with default -march // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e76 | FileCheck -check-prefix=MCPU-SIFIVE-E76 %s // MCPU-SIFIVE-E76: "-nostdsysteminc" "-target-cpu" "sifive-e76" // MCPU-SIFIVE-E76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" @@ -390,7 +390,7 @@ // MCPU-SIFIVE-E76: "-target-feature" "+zicsr" "-target-feature" "+zifencei" // MCPU-SIFIVE-E76: "-target-abi" "ilp32f" -// mcpu with mabi option +// -mcpu with -mabi option // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-u74 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-U74 %s // MCPU-ABI-SIFIVE-U74: "-nostdsysteminc" "-target-cpu" "sifive-u74" // MCPU-ABI-SIFIVE-U74: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" @@ -398,13 +398,13 @@ // MCPU-ABI-SIFIVE-U74: "-target-feature" "+zicsr" "-target-feature" "+zifencei" // MCPU-ABI-SIFIVE-U74: "-target-abi" "lp64" -// march overwrite mcpu's default march +// -march overwrite -mcpu's default -march // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=sifive-e31 -march=rv32imc | FileCheck -check-prefix=MCPU-MARCH %s // MCPU-MARCH: "-nostdsysteminc" "-target-cpu" "sifive-e31" "-target-feature" "+m" "-target-feature" "+c" // MCPU-MARCH: "-target-abi" "ilp32" -// Check interaction between mcpu and mtune, mtune won't affect arch related -// target feature, but mcpu will. +// Check interaction between -mcpu and mtune, -mtune won't affect arch related +// target feature, but -mcpu will. // // In this case, sifive-e31 is rv32imac, sifive-e76 is rv32imafc, so F-extension // should not enabled. @@ -418,7 +418,7 @@ // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei" // MTUNE-E31-MCPU-E76-SAME: "-tune-cpu" "sifive-e76" -// mcpu with default march include experimental extensions +// -mcpu with default -march include experimental extensions // RUN: %clang -target riscv64 -### -c %s 2>&1 -menable-experimental-extensions -mcpu=sifive-x280 | FileCheck -check-prefix=MCPU-SIFIVE-X280 %s // MCPU-SIFIVE-X280: "-nostdsysteminc" "-target-cpu" "sifive-x280" // MCPU-SIFIVE-X280-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
