================ @@ -1003,15 +1003,29 @@ Arm and AArch64 Support `as specified here <https://github.com/ARM-software/acle/blob/main/main/acle.md#modal-8-bit-floating-point-extensions>`_ is now available. - Support has been added for the following processors (command-line identifiers in parentheses): + - Arm Cortex-A320 (``cortex-a320``) + - For ARM targets, cc1as now considers the FPU's features for the selected CPU or Architecture. - The ``+nosimd`` attribute is now fully supported for ARM. Previously, this had no effect when being used with ARM targets, however this will now disable NEON instructions being generated. The ``simd`` option is also now printed when the ``--print-supported-extensions`` option is used. - When a feature that depends on NEON (``simd``) is used, NEON is now automatically enabled. - When NEON is disabled (``+nosimd``), all features that depend on NEON will now be disabled. -- Support for __ptrauth type qualifier has been added. +- Pointer authentication + + - Support for __ptrauth type qualifier has been added. + - Objective-C adoption of pointer authentication + + - ``isa`` and ``super`` pointers are protected with address diversity and separate + usage specific discriminators. + - methodlist pointers and content are protected with address diversity and methodlist + pointers have a usage specific discriminator. + - ``class_ro_t`` pointers are protected with address diversity and usage specific + discriminators. + - ``SEL`` typed ivars are protected with address diversity and usage specific + discriminators. ---------------- rjmccall wrote:
Does the `SEL` thing need more of a release note? The rest of this is all implementation-level, but `SEL` being implicitly `__ptrauth`ed makes it user-affecting, and we probably need to talk through it for the corner-case user using arm64e ObjC. https://github.com/llvm/llvm-project/pull/147899 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
