https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/148563
The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. The extension includes only two instructions: one for converting from f32 to f16, and another for converting from f16 to f32. This patch only implements MC support for XAndesBFHCvt. >From 766e2c690a7f4f08e5bf3fb6d9e88a5e287f4e7a Mon Sep 17 00:00:00 2001 From: Jim Lin <j...@andestech.com> Date: Mon, 14 Jul 2025 09:36:39 +0800 Subject: [PATCH] [RISCV] Add Andes XAndesBFHCvt (Andes Scalar BFLOAT16) extension The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. The extension includes only two instructions: one for converting from f32 to f16, and another for converting from f16 to f32. This patch only implements MC support for XAndesBFHCvt. --- .../Driver/print-supported-extensions-riscv.c | 1 + .../riscv-target-features-andes.c | 9 +++++++ llvm/docs/RISCVUsage.rst | 3 +++ llvm/docs/ReleaseNotes.md | 1 + .../RISCV/Disassembler/RISCVDisassembler.cpp | 3 ++- llvm/lib/Target/RISCV/RISCVFeatures.td | 8 +++++++ llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td | 24 +++++++++++++++++++ llvm/test/CodeGen/RISCV/attributes.ll | 4 ++++ llvm/test/CodeGen/RISCV/features-info.ll | 1 + .../TargetParser/RISCVISAInfoTest.cpp | 1 + 10 files changed, 54 insertions(+), 1 deletion(-) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index b87f0cb568e00..2503f2473d64a 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -158,6 +158,7 @@ // CHECK-NEXT: svnapot 1.0 'Svnapot' (NAPOT Translation Contiguity) // CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory Types) // CHECK-NEXT: svvptc 1.0 'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid) +// CHECK-NEXT: xandesbfhcvt 5.0 'XAndesBFHCvt' (Andes Scalar BFLOAT16 Conversion Extension) // CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension) // CHECK-NEXT: xandesvbfhcvt 5.0 'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension) // CHECK-NEXT: xandesvdot 5.0 'XAndesVDot' (Andes Vector Dot Product Extension) diff --git a/clang/test/Preprocessor/riscv-target-features-andes.c b/clang/test/Preprocessor/riscv-target-features-andes.c index 083deb02a2679..f7981bb52de6d 100644 --- a/clang/test/Preprocessor/riscv-target-features-andes.c +++ b/clang/test/Preprocessor/riscv-target-features-andes.c @@ -4,6 +4,7 @@ // RUN: -o - | FileCheck %s // CHECK-NOT: __riscv_xandesperf {{.*$}} +// CHECK-NOT: __riscv_xandesbfhcvt {{.*$}} // CHECK-NOT: __riscv_xandesvbfhcvt {{.*$}} // CHECK-NOT: __riscv_xandesvsintload {{.*$}} // CHECK-NOT: __riscv_xandesvpackfph {{.*$}} @@ -17,6 +18,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-XANDESPERF %s // CHECK-XANDESPERF: __riscv_xandesperf 5000000{{$}} +// RUN: %clang --target=riscv32 \ +// RUN: -march=rv32i_xandesbfhcvt -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESBFHCVT %s +// RUN: %clang --target=riscv64 \ +// RUN: -march=rv64i_xandesbfhcvt -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-XANDESBFHCVT %s +// CHECK-XANDESBFHCVT: __riscv_xandesbfhcvt 5000000{{$}} + // RUN: %clang --target=riscv32 \ // RUN: -march=rv32i_xandesvbfhcvt -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-XANDESVBFHCVT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 158a20cce7f85..9f6ac558b6f7c 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -516,6 +516,9 @@ The current vendor extensions supported are: ``XAndesPerf`` LLVM implements `version 5.0.0 of the Andes Performance Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification. +``XAndesBFHCvt`` + LLVM implements `version 5.0.0 of the Andes Scalar BFLOAT16 Conversion Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification. + ``XAndesVBFHCvt`` LLVM implements `version 5.0.0 of the Andes Vector BFLOAT16 Conversion Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>`__ by Andes Technology. All instructions are prefixed with `nds.` as described in the specification. diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index daf822388a2ff..43ed85db0315c 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -214,6 +214,7 @@ Changes to the RISC-V Backend * `-mcpu=andes-ax45mpv` was added. * Removed -mattr=+no-rvc-hints that could be used to disable parsing and generation of RVC hints. * Adds assembler support for the Andes `XAndesvsintload` (Andes Vector INT4 Load extension). +* Adds assembler support for the Andes `XAndesbfhcvt` (Andes Scalar BFLOAT16 Conversion extension). Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index b723958a6ff28..fa7bcfa0e8132 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -774,7 +774,8 @@ static constexpr FeatureBitset XTHeadGroup = { RISCV::FeatureVendorXTHeadVdot}; static constexpr FeatureBitset XAndesGroup = { - RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesVBFHCvt, + RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesBFHCvt, + RISCV::FeatureVendorXAndesVBFHCvt, RISCV::FeatureVendorXAndesVSIntLoad, RISCV::FeatureVendorXAndesVPackFPH, RISCV::FeatureVendorXAndesVDot}; diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index cb704f56d9ccd..3fb7314a1a413 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1599,6 +1599,14 @@ def HasVendorXAndesPerf AssemblerPredicate<(all_of FeatureVendorXAndesPerf), "'XAndesPerf' (Andes Performance Extension)">; +def FeatureVendorXAndesBFHCvt + : RISCVExtension<5, 0, "Andes Scalar BFLOAT16 Conversion Extension", + [FeatureStdExtF]>; +def HasVendorXAndesBFHCvt + : Predicate<"Subtarget->hasVendorXAndesBFHCvt()">, + AssemblerPredicate<(all_of FeatureVendorXAndesBFHCvt), + "'XAndesBFHCvt' (Andes Scalar BFLOAT16 Conversion Extension)">; + def FeatureVendorXAndesVBFHCvt : RISCVExtension<5, 0, "Andes Vector BFLOAT16 Conversion Extension", [FeatureStdExtZve32f]>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td index ec38201cd28c6..38992b6c05d08 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td @@ -348,6 +348,17 @@ class NDSRVInstSDGP<bits<3> funct3, string opcodestr> let mayStore = 1; } +class NDSRVInstBFHCvt<bits<7> funct7, bits<5> rs1val, DAGOperand rdty, + DAGOperand rs2ty, string opcodestr> + : RVInstR<funct7, 0b100, OPC_CUSTOM_2, (outs rdty:$rd), + (ins rs2ty:$rs2), opcodestr, "$rd, $rs2"> { + let rs1 = rs1val; + let hasSideEffects = 0; + let mayLoad = 0; + let mayStore = 0; + let mayRaiseFPException = 1; +} + class NDSRVInstVFPMAD<bits<6> funct6, string opcodestr> : RVInst<(outs VR:$vd), (ins VR:$vs2, FPR32:$rs1, VMaskOp:$vm), opcodestr # "." # "vf", "$vd, $rs1, $vs2$vm", [], InstFormatR>, @@ -630,6 +641,19 @@ def NDS_LDGP : NDSRVInstLDGP<0b011, "nds.ldgp">; def NDS_SDGP : NDSRVInstSDGP<0b111, "nds.sdgp">; } // Predicates = [HasVendorXAndesPerf, IsRV64] +//===----------------------------------------------------------------------===// +// XAndesBFHCvt +//===----------------------------------------------------------------------===// + +let Predicates = [HasVendorXAndesBFHCvt] in { +def NDS_FCVT_S_BF16 : NDSRVInstBFHCvt<0b0000000, 0b00010, + FPR32, FPR16, "nds.fcvt.s.bf16">, + Sched<[WriteFCvtF16ToF32, ReadFCvtF16ToF32]>; +def NDS_FCVT_BF16_S : NDSRVInstBFHCvt<0b0000000, 0b00011, + FPR16, FPR32, "nds.fcvt.bf16.s">, + Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>; +} + //===----------------------------------------------------------------------===// // XAndesVBFHCvt //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 43e16606aae73..d566069f4200b 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -106,6 +106,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisls %s -o - | FileCheck --check-prefix=RV32XQCISLS %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisync %s -o - | FileCheck --check-prefix=RV32XQCISYNC %s ; RUN: llc -mtriple=riscv32 -mattr=+xandesperf %s -o - | FileCheck --check-prefix=RV32XANDESPERF %s +; RUN: llc -mtriple=riscv32 -mattr=+xandesbfhcvt %s -o - | FileCheck --check-prefix=RV32XANDESBFHCVT %s ; RUN: llc -mtriple=riscv32 -mattr=+xandesvbfhcvt %s -o - | FileCheck --check-prefix=RV32XANDESVBFHCVT %s ; RUN: llc -mtriple=riscv32 -mattr=+xandesvsintload %s -o - | FileCheck --check-prefix=RV32XANDESVSINTLOAD %s ; RUN: llc -mtriple=riscv32 -mattr=+xandesvdot %s -o - | FileCheck --check-prefix=RV32XANDESVDOT %s @@ -262,6 +263,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+xtheadsync %s -o - | FileCheck --check-prefix=RV64XTHEADSYNC %s ; RUN: llc -mtriple=riscv64 -mattr=+xtheadvdot %s -o - | FileCheck --check-prefixes=CHECK,RV64XTHEADVDOT %s ; RUN: llc -mtriple=riscv64 -mattr=+xandesperf %s -o - | FileCheck --check-prefix=RV64XANDESPERF %s +; RUN: llc -mtriple=riscv64 -mattr=+xandesbfhcvt %s -o - | FileCheck --check-prefix=RV64XANDESBFHCVT %s ; RUN: llc -mtriple=riscv64 -mattr=+xandesvbfhcvt %s -o - | FileCheck --check-prefix=RV64XANDESVBFHCVT %s ; RUN: llc -mtriple=riscv64 -mattr=+xandesvsintload %s -o - | FileCheck --check-prefix=RV64XANDESVSINTLOAD %s ; RUN: llc -mtriple=riscv64 -mattr=+xandesvdot %s -o - | FileCheck --check-prefix=RV64XANDESVDOT %s @@ -462,6 +464,7 @@ ; RV32XQCISLS: .attribute 5, "rv32i2p1_xqcisls0p2" ; RV32XQCISYNC: attribute 5, "rv32i2p1_zca1p0_xqcisync0p3" ; RV32XANDESPERF: .attribute 5, "rv32i2p1_xandesperf5p0" +; RV32XANDESBFHCVT: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0" ; RV32XANDESVBFHCVT: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xandesvbfhcvt5p0" ; RV32XANDESVSINTLOAD: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvsintload5p0" ; RV32XANDESVDOT: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvdot5p0" @@ -620,6 +623,7 @@ ; RV64XTHEADSYNC: .attribute 5, "rv64i2p1_xtheadsync1p0" ; RV64XTHEADVDOT: .attribute 5, "rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0" ; RV64XANDESPERF: .attribute 5, "rv64i2p1_xandesperf5p0" +; RV64XANDESBFHCVT: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_xandesbfhcvt5p0" ; RV64XANDESVBFHCVT: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xandesvbfhcvt5p0" ; RV64XANDESVSINTLOAD: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvsintload5p0" ; RV64XANDESVDOT: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xandesvdot5p0" diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 26f5ab10f6c36..b94665b718ae7 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -173,6 +173,7 @@ ; CHECK-NEXT: ventana-veyron - Ventana Veyron-Series processors. ; CHECK-NEXT: vl-dependent-latency - Latency of vector instructions is dependent on the dynamic value of vl. ; CHECK-NEXT: vxrm-pipeline-flush - VXRM writes causes pipeline flush. +; CHECK-NEXT: xandesbfhcvt - 'XAndesBFHCvt' (Andes Scalar BFLOAT16 Conversion Extension). ; CHECK-NEXT: xandesperf - 'XAndesPerf' (Andes Performance Extension). ; CHECK-NEXT: xandesvbfhcvt - 'XAndesVBFHCvt' (Andes Vector BFLOAT16 Conversion Extension). ; CHECK-NEXT: xandesvdot - 'XAndesVDot' (Andes Vector Dot Product Extension). diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 9780eba5dc7a7..319538eaea135 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1129,6 +1129,7 @@ R"(All available -march extensions for RISC-V svnapot 1.0 svpbmt 1.0 svvptc 1.0 + xandesbfhcvt 5.0 xandesperf 5.0 xandesvbfhcvt 5.0 xandesvdot 5.0 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
