llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: Jim Lin (tclin914) <details> <summary>Changes</summary> This patch implements clang intrinsic support for XAndesVSIntLoad. The document for the intrinsics can be found at: https://github.com/andestech/andes-vector-intrinsic-doc/blob/ast-v5_4_0-release-v5/auto-generated/andes-v5/intrinsic_funcs/04_andes_vector_int4_load_extension.adoc --- Patch is 104.76 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/147767.diff 9 Files Affected: - (modified) clang/include/clang/Basic/riscv_andes_vector.td (+29) - (added) clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c (+148) - (added) clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c (+148) - (added) clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c (+78) - (added) clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vlnu8.c (+78) - (added) clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vln8.c (+288) - (added) clang/test/CodeGen/RISCV/andes-intrinsics/policy/non-overloaded/nds_vlnu8.c (+288) - (added) clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vln8.c (+288) - (added) clang/test/CodeGen/RISCV/andes-intrinsics/policy/overloaded/nds_vlnu8.c (+288) ``````````diff diff --git a/clang/include/clang/Basic/riscv_andes_vector.td b/clang/include/clang/Basic/riscv_andes_vector.td index 67e07f8396ade..d86ee16eaa569 100644 --- a/clang/include/clang/Basic/riscv_andes_vector.td +++ b/clang/include/clang/Basic/riscv_andes_vector.td @@ -64,6 +64,35 @@ let RequiredFeatures = ["xandesvbfhcvt"], } } +// Andes Vector INT4 Load Extension (XAndesVSIntLoad) + +let SupportOverloading = false, + UnMaskedPolicyScheme = HasPassthruOperand in { + multiclass RVVVLN8Builtin { + let Name = NAME # "_v", + IRName = "nds_vln", + MaskedIRName = "nds_vln_mask", + OverloadedName = NAME in + def : RVVOutOp0Builtin<"v", "vPC0", "c">; + } +} + +let SupportOverloading = false, + UnMaskedPolicyScheme = HasPassthruOperand in { + multiclass RVVVLNU8Builtin { + let Name = NAME # "_v", + IRName = "nds_vlnu", + MaskedIRName = "nds_vlnu_mask", + OverloadedName = NAME in + def : RVVOutOp0Builtin<"Uv", "UvPC0", "c">; + } +} + +let RequiredFeatures = ["xandesvsintload"] in { +defm nds_vln8 : RVVVLN8Builtin; +defm nds_vlnu8 : RVVVLNU8Builtin; +} + // Andes Vector Packed FP16 Extension (XAndesVPackFPH) multiclass RVVFPMAD { diff --git a/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c b/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c new file mode 100644 index 0000000000000..5f8ec02f48670 --- /dev/null +++ b/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vln8.c @@ -0,0 +1,148 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \ +// RUN: -target-feature +xandesvsintload -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include <andes_vector.h> + +// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.nds.vln.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] +// +vint8mf8_t test_nds_vln8_v_i8mf8(const void *base, size_t vl) { + return __riscv_nds_vln8_v_i8mf8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.nds.vln.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] +// +vint8mf4_t test_nds_vln8_v_i8mf4(const void *base, size_t vl) { + return __riscv_nds_vln8_v_i8mf4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.nds.vln.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] +// +vint8mf2_t test_nds_vln8_v_i8mf2(const void *base, size_t vl) { + return __riscv_nds_vln8_v_i8mf2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.nds.vln.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] +// +vint8m1_t test_nds_vln8_v_i8m1(const void *base, size_t vl) { + return __riscv_nds_vln8_v_i8m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.nds.vln.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] +// +vint8m2_t test_nds_vln8_v_i8m2(const void *base, size_t vl) { + return __riscv_nds_vln8_v_i8m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_nds_vln8_v_i8m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.nds.vln.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] +// +vint8m4_t test_nds_vln8_v_i8m4(const void *base, size_t vl) { + return __riscv_nds_vln8_v_i8m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_nds_vln8_v_i8m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.nds.vln.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] +// +vint8m8_t test_nds_vln8_v_i8m8(const void *base, size_t vl) { + return __riscv_nds_vln8_v_i8m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_m +// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] +// +vint8mf8_t test_nds_vln8_v_i8mf8_m(vbool64_t mask, const void *base, size_t vl) { + return __riscv_nds_vln8_v_i8mf8_m(mask, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_m +// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] +// +vint8mf4_t test_nds_vln8_v_i8mf4_m(vbool32_t mask, const void *base, size_t vl) { + return __riscv_nds_vln8_v_i8mf4_m(mask, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_nds_vln8_v_i8mf2_m +// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.nds.vln.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] +// +vint8mf2_t test_nds_vln8_v_i8mf2_m(vbool16_t mask, const void *base, size_t vl) { + return __riscv_nds_vln8_v_i8mf2_m(mask, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_nds_vln8_v_i8m1_m +// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.nds.vln.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] +// +vint8m1_t test_nds_vln8_v_i8m1_m(vbool8_t mask, const void *base, size_t vl) { + return __riscv_nds_vln8_v_i8m1_m(mask, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_nds_vln8_v_i8m2_m +// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.nds.vln.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] +// +vint8m2_t test_nds_vln8_v_i8m2_m(vbool4_t mask, const void *base, size_t vl) { + return __riscv_nds_vln8_v_i8m2_m(mask, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_nds_vln8_v_i8m4_m +// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.nds.vln.mask.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr [[BASE]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] +// +vint8m4_t test_nds_vln8_v_i8m4_m(vbool2_t mask, const void *base, size_t vl) { + return __riscv_nds_vln8_v_i8m4_m(mask, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_nds_vln8_v_i8m8_m +// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.nds.vln.mask.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr [[BASE]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] +// +vint8m8_t test_nds_vln8_v_i8m8_m(vbool1_t mask, const void *base, size_t vl) { + return __riscv_nds_vln8_v_i8m8_m(mask, base, vl); +} diff --git a/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c b/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c new file mode 100644 index 0000000000000..98940366aa22c --- /dev/null +++ b/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/non-overloaded/nds_vlnu8.c @@ -0,0 +1,148 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \ +// RUN: -target-feature +xandesvsintload -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include <andes_vector.h> + +// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] +// +vuint8mf8_t test_nds_vlnu8_v_u8mf8(const void *base, size_t vl) { + return __riscv_nds_vlnu8_v_u8mf8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] +// +vuint8mf4_t test_nds_vlnu8_v_u8mf4(const void *base, size_t vl) { + return __riscv_nds_vlnu8_v_u8mf4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] +// +vuint8mf2_t test_nds_vlnu8_v_u8mf2(const void *base, size_t vl) { + return __riscv_nds_vlnu8_v_u8mf2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] +// +vuint8m1_t test_nds_vlnu8_v_u8m1(const void *base, size_t vl) { + return __riscv_nds_vlnu8_v_u8m1(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] +// +vuint8m2_t test_nds_vlnu8_v_u8m2(const void *base, size_t vl) { + return __riscv_nds_vlnu8_v_u8m2(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] +// +vuint8m4_t test_nds_vlnu8_v_u8m4(const void *base, size_t vl) { + return __riscv_nds_vlnu8_v_u8m4(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8 +// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr [[BASE]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] +// +vuint8m8_t test_nds_vlnu8_v_u8m8(const void *base, size_t vl) { + return __riscv_nds_vlnu8_v_u8m8(base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_nds_vlnu8_v_u8mf8_m +// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.nds.vlnu.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] +// +vuint8mf8_t test_nds_vlnu8_v_u8mf8_m(vbool64_t mask, const void *base, size_t vl) { + return __riscv_nds_vlnu8_v_u8mf8_m(mask, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_nds_vlnu8_v_u8mf4_m +// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.nds.vlnu.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] +// +vuint8mf4_t test_nds_vlnu8_v_u8mf4_m(vbool32_t mask, const void *base, size_t vl) { + return __riscv_nds_vlnu8_v_u8mf4_m(mask, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_nds_vlnu8_v_u8mf2_m +// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.nds.vlnu.mask.nxv4i8.p0.i64(<vscale x 4 x i8> poison, ptr [[BASE]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] +// +vuint8mf2_t test_nds_vlnu8_v_u8mf2_m(vbool16_t mask, const void *base, size_t vl) { + return __riscv_nds_vlnu8_v_u8mf2_m(mask, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_nds_vlnu8_v_u8m1_m +// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.nds.vlnu.mask.nxv8i8.p0.i64(<vscale x 8 x i8> poison, ptr [[BASE]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret <vscale x 8 x i8> [[TMP0]] +// +vuint8m1_t test_nds_vlnu8_v_u8m1_m(vbool8_t mask, const void *base, size_t vl) { + return __riscv_nds_vlnu8_v_u8m1_m(mask, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_nds_vlnu8_v_u8m2_m +// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i8> @llvm.riscv.nds.vlnu.mask.nxv16i8.p0.i64(<vscale x 16 x i8> poison, ptr [[BASE]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret <vscale x 16 x i8> [[TMP0]] +// +vuint8m2_t test_nds_vlnu8_v_u8m2_m(vbool4_t mask, const void *base, size_t vl) { + return __riscv_nds_vlnu8_v_u8m2_m(mask, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_nds_vlnu8_v_u8m4_m +// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i8> @llvm.riscv.nds.vlnu.mask.nxv32i8.p0.i64(<vscale x 32 x i8> poison, ptr [[BASE]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret <vscale x 32 x i8> [[TMP0]] +// +vuint8m4_t test_nds_vlnu8_v_u8m4_m(vbool2_t mask, const void *base, size_t vl) { + return __riscv_nds_vlnu8_v_u8m4_m(mask, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_nds_vlnu8_v_u8m8_m +// CHECK-RV64-SAME: (<vscale x 64 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i8> @llvm.riscv.nds.vlnu.mask.nxv64i8.p0.i64(<vscale x 64 x i8> poison, ptr [[BASE]], <vscale x 64 x i1> [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret <vscale x 64 x i8> [[TMP0]] +// +vuint8m8_t test_nds_vlnu8_v_u8m8_m(vbool1_t mask, const void *base, size_t vl) { + return __riscv_nds_vlnu8_v_u8m8_m(mask, base, vl); +} diff --git a/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c b/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c new file mode 100644 index 0000000000000..71e2414ac5804 --- /dev/null +++ b/clang/test/CodeGen/RISCV/andes-intrinsics/non-policy/overloaded/nds_vln8.c @@ -0,0 +1,78 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +zve64x \ +// RUN: -target-feature +xandesvsintload -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include <andes_vector.h> + +// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_nds_vln8_v_i8mf8_m +// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.nds.vln.mask.nxv1i8.p0.i64(<vscale x 1 x i8> poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] +// +vint8mf8_t test_nds_vln8_v_i8mf8_m(vbool64_t mask, const void *base, size_t vl) { + return __riscv_nds_vln8(mask, base, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_nds_vln8_v_i8mf4_m +// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], ptr noundef [[BASE:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.nds.vln.mask.nxv2i8.p0.i64(<vscale x 2 x i8> poison, ptr [[BASE]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret <vsc... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/147767 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
