github-actions[bot] wrote:
<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
<details>
<summary>
You can test this locally with the following command:
</summary>
``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions c,h,cpp --
clang/test/Driver/print-supported-extensions-riscv.c
clang/test/Preprocessor/riscv-target-features.c
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp llvm/lib/Target/RISCV/RISCVInstrInfo.h
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
``````````
</details>
<details>
<summary>
View the diff from clang-format here.
</summary>
``````````diff
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 0e9ee0834..0f3e08083 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -789,8 +789,9 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
RISCVCC::CondCode CC;
getOperandsForBranch(MI.getOperand(0).getReg(), CC, LHS, RHS, *MRI);
- auto Bcc = MIB.buildInstr(RISCVCC::getBrCond(*Subtarget, CC), {}, {LHS,
RHS})
- .addMBB(MI.getOperand(1).getMBB());
+ auto Bcc =
+ MIB.buildInstr(RISCVCC::getBrCond(*Subtarget, CC), {}, {LHS, RHS})
+ .addMBB(MI.getOperand(1).getMBB());
MI.eraseFromParent();
return constrainSelectedInstRegOperands(*Bcc, TII, TRI, RBI);
}
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 664677ada..0e31ac890 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -21413,7 +21413,8 @@ EmitLoweredCascadedSelect(MachineInstr &First,
MachineInstr &Second,
Register FLHS = First.getOperand(1).getReg();
Register FRHS = First.getOperand(2).getReg();
// Insert appropriate branch.
- BuildMI(FirstMBB, DL, TII.get(RISCVCC::getBrCond(Subtarget, FirstCC,
First.getOpcode())))
+ BuildMI(FirstMBB, DL,
+ TII.get(RISCVCC::getBrCond(Subtarget, FirstCC, First.getOpcode())))
.addReg(FLHS)
.addReg(FRHS)
.addMBB(SinkMBB);
@@ -21561,12 +21562,14 @@ static MachineBasicBlock
*emitSelectPseudo(MachineInstr &MI,
// Insert appropriate branch.
if (MI.getOperand(2).isImm())
- BuildMI(HeadMBB, DL, TII.get(RISCVCC::getBrCond(Subtarget, CC,
MI.getOpcode(), true)))
+ BuildMI(HeadMBB, DL,
+ TII.get(RISCVCC::getBrCond(Subtarget, CC, MI.getOpcode(), true)))
.addReg(LHS)
.addImm(MI.getOperand(2).getImm())
.addMBB(TailMBB);
else
- BuildMI(HeadMBB, DL, TII.get(RISCVCC::getBrCond(Subtarget, CC,
MI.getOpcode())))
+ BuildMI(HeadMBB, DL,
+ TII.get(RISCVCC::getBrCond(Subtarget, CC, MI.getOpcode())))
.addReg(LHS)
.addReg(RHS)
.addMBB(TailMBB);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index d425df2e1..361269af5 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1029,7 +1029,8 @@ static void parseCondBranch(MachineInstr &LastInst,
MachineBasicBlock *&Target,
Cond.push_back(LastInst.getOperand(1));
}
-unsigned RISCVCC::getBrCond(const RISCVSubtarget &STI, CondCode CC, unsigned
SelectOpc, bool Imm) {
+unsigned RISCVCC::getBrCond(const RISCVSubtarget &STI, CondCode CC,
+ unsigned SelectOpc, bool Imm) {
switch (SelectOpc) {
default:
switch (CC) {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 15e790cd0..060d4cbb4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -45,7 +45,8 @@ enum CondCode {
};
CondCode getOppositeBranchCondition(CondCode);
-unsigned getBrCond(const RISCVSubtarget &STI, CondCode CC, unsigned SelectOpc
= 0, bool Imm = false);
+unsigned getBrCond(const RISCVSubtarget &STI, CondCode CC,
+ unsigned SelectOpc = 0, bool Imm = false);
} // end of namespace RISCVCC
``````````
</details>
https://github.com/llvm/llvm-project/pull/146858
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