https://github.com/CarolineConcatto updated
https://github.com/llvm/llvm-project/pull/146353
>From 27917c4896f31bc3ffd7e466ff9bf1cea15ba476 Mon Sep 17 00:00:00 2001
From: CarolineConcatto <caroline.conca...@arm.com>
Date: Mon, 30 Jun 2025 12:15:25 +0000
Subject: [PATCH 1/3] [AArch64] Mark aarch64_set_fpmr as IntrWriteMem
llvm.aarch64.set.fpmr only writes to inaccessible memory.
Tag it with the IntrWriteMem and IntrInaccessibleMemOnly properties so the
optimiser can treat it as a pure write.
The original patch did not add this property, causing the intrinsic
to be conservatively treated as readwrite. This commit fixes that.
---
.../test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c | 3 +++
.../test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c | 4 ++++
.../test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c | 4 ++++
.../test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c | 4 ++++
.../CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c | 5 +++++
.../test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c | 5 +++++
.../test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c | 5 +++++
.../test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c | 5 +++++
.../test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c | 5 +++++
.../test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c | 5 +++++
llvm/include/llvm/IR/IntrinsicsAArch64.td | 2 +-
11 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
index 9913c54567719..f7030b62c0f8e 100644
--- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
+++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
@@ -330,3 +330,6 @@ mfloat8x8_t test_vcvt_mf8_f16_fpm(float16x4_t vn,
float16x4_t vm, fpm_t fpm) {
mfloat8x16_t test_vcvtq_mf8_f16_fpm(float16x8_t vn, float16x8_t vm, fpm_t fpm)
{
return vcvtq_mf8_f16_fpm(vn, vm, fpm);
}
+
+// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR1:#.*]]
+// CHECK: attributes [[ATTR1]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: write) }
diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
index 44db59df6c1c4..c9c4e277440ae 100644
--- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
+++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
@@ -83,6 +83,8 @@ float16x4_t test_vdot_lane_f16(float16x4_t vd, mfloat8x8_t
vn, mfloat8x8_t vm, f
return vdot_lane_f16_mf8_fpm(vd, vn, vm, 3, fpmr);
}
+// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR1:#.*]]
+
// CHECK-LABEL: define dso_local <4 x half> @test_vdot_laneq_f16(
// CHECK-SAME: <4 x half> noundef [[VD:%.*]], <8 x i8> [[VN:%.*]], <16 x i8>
[[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -268,3 +270,5 @@ float32x4_t test_vdotq_lane_f32(float32x4_t vd,
mfloat8x16_t vn, mfloat8x8_t vm,
float32x4_t test_vdotq_laneq_f32(float32x4_t vd, mfloat8x16_t vn, mfloat8x16_t
vm, fpm_t fpmr) {
return vdotq_laneq_f32_mf8_fpm(vd, vn, vm, 3, fpmr);
}
+
+// CHECK: attributes [[ATTR1]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: write) }
diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
index d4f074a92b05b..222a8e7272745 100644
--- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
+++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
@@ -154,6 +154,8 @@ float16x8_t test_vmlalb_lane(float16x8_t vd, mfloat8x16_t
vn, mfloat8x8_t vm, fp
return vmlalbq_lane_f16_mf8_fpm(vd, vn, vm, 0, fpm);
}
+// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR1:#.*]]
+
// CHECK-LABEL: define dso_local <8 x half> @test_vmlalb_laneq(
// CHECK-SAME: <8 x half> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8>
[[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -379,3 +381,5 @@ float32x4_t test_vmlalltt_lane(float32x4_t vd, mfloat8x16_t
vn, mfloat8x8_t vm,
float32x4_t test_vmlalltt_laneq(float32x4_t vd, mfloat8x16_t vn, mfloat8x16_t
vm, fpm_t fpm) {
return vmlallttq_laneq_f32_mf8_fpm(vd, vn, vm, 15, fpm);
}
+
+// CHECK: attributes [[ATTR1]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: write) }
diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
index ae2e780f84cfe..3dbeb0aab6e25 100644
--- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
+++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
@@ -32,6 +32,8 @@ svmfloat8_t test_cvt_f16_x2(svfloat16x2_t zn, fpm_t fpmr)
__arm_streaming {
return SVE_ACLE_FUNC(svcvt_mf8,_f16_x2,_fpm)(zn, fpmr);
}
+// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR1:#.*]]
+
// CHECK-LABEL: @test_cvt_f32_x4(
// CHECK-NEXT: entry:
// CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR:%.*]])
@@ -207,3 +209,5 @@ svbfloat16x2_t test_cvtl1_bf16_x2(svmfloat8_t zn, fpm_t
fpmr) __arm_streaming {
svbfloat16x2_t test_cvtl2_bf16_x2(svmfloat8_t zn, fpm_t fpmr) __arm_streaming
{
return SVE_ACLE_FUNC(svcvtl2_bf16,_mf8,_x2_fpm)(zn, fpmr);
}
+
+// CHECK: attributes [[ATTR1]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: write) }
diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
index 95d6383ab30ef..c11baf60c6b48 100644
--- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
+++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
@@ -35,6 +35,8 @@ void test_svmopa_za16_mf8_m(svbool_t pn, svbool_t pm,
svmfloat8_t zn,
SVE_ACLE_FUNC(svmopa_za16,_mf8,_m_fpm)(1, pn, pm, zn, zm, fpmr);
}
+// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR1:#.*]]
+//
// CHECK-LABEL: define dso_local void @test_svmopa_za32_mf8_m(
// CHECK-SAME: <vscale x 16 x i1> [[PN:%.*]], <vscale x 16 x i1> [[PM:%.*]],
<vscale x 16 x i8> [[ZN:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef
[[FPMR:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -53,3 +55,6 @@ void test_svmopa_za32_mf8_m(svbool_t pn, svbool_t pm,
svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpmr) __arm_streaming
__arm_inout("za") {
SVE_ACLE_FUNC(svmopa_za32,_mf8,_m_fpm)(3, pn, pm, zn, zm, fpmr);
}
+
+
+// CHECK: attributes [[ATTR1]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: write) }
diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
index d603045edf282..ef8319ffa6372 100644
--- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
+++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
@@ -35,6 +35,8 @@ void test_svmla_lane_za16_vg2x1(uint32_t slice, svmfloat8_t
zn, svmfloat8_t zm,
SME_ACLE_FUNC(svmla_lane_za16,_mf8,_vg2x1_fpm,,)(slice, zn, zm, 0, fpm);
}
+// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR1:#.*]]
+
// CHECK-LABEL: define dso_local void @test_svmla_lane_za16_vg2x2(
// CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8>
[[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8>
[[ZM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -314,3 +316,6 @@ void test_svmla_multi_za32_vg4x2(uint32_t slice,
svmfloat8x2_t zn, svmfloat8x2_t
void test_svmla_multi_za32_vg4x4(uint32_t slice, svmfloat8x4_t zn,
svmfloat8x4_t zm, fpm_t fpm) __arm_streaming __arm_inout("za") {
SME_ACLE_FUNC(svmla_za32,_mf8,_vg4x4_fpm,,)(slice, zn, zm, fpm);
}
+
+
+// CHECK: attributes [[ATTR1]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: write) }
diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
index c026b8aa216f3..7187831f2a0a4 100644
--- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
+++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
@@ -46,6 +46,8 @@ svbfloat16_t test_svcvt1_bf16_mf8(svmfloat8_t zn, fpm_t fpm)
STREAMING {
return SVE_ACLE_FUNC(svcvt1_bf16,_mf8,_fpm)(zn, fpm);
}
+// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR1:#.*]]
+
// CHECK-LABEL: define dso_local <vscale x 8 x bfloat> @test_svcvt2_bf16_mf8(
// CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]])
#[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -171,3 +173,6 @@ svfloat16_t test_svcvtlt1_f16_mf8(svmfloat8_t zn, fpm_t
fpm) STREAMING {
svfloat16_t test_svcvtlt2_f16_mf8(svmfloat8_t zn, fpm_t fpm) STREAMING {
return SVE_ACLE_FUNC(svcvtlt2_f16,_mf8,_fpm)(zn, fpm);
}
+
+
+// CHECK: attributes [[ATTR1]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: write) }
diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
index ed5b0ce02af4b..0ffad95720954 100644
--- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
+++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
@@ -46,6 +46,8 @@ svmfloat8_t test_svcvtn_f8_bf16(svbfloat16x2_t zn_zm, fpm_t
fpm) STREAMING {
return SVE_ACLE_FUNC(svcvtn_mf8,_bf16_x2,_fpm)(zn_zm, fpm);
}
+// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR1:#.*]]
+
// CHECK-LABEL: define dso_local <vscale x 16 x i8> @test_svcvtn_f8_f16(
// CHECK-SAME: <vscale x 8 x half> [[ZN_ZM_COERCE0:%.*]], <vscale x 8 x half>
[[ZN_ZM_COERCE1:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -99,3 +101,6 @@ svmfloat8_t test_svcvtnb_f8_f32(svfloat32x2_t zn_zm, fpm_t
fpm) STREAMING {
svmfloat8_t test_svcvtnt_f8_f32(svmfloat8_t zd, svfloat32x2_t zn_zm, fpm_t
fpm) STREAMING {
return SVE_ACLE_FUNC(svcvtnt_mf8,_f32_x2,_fpm)(zd, zn_zm, fpm);
}
+
+
+// CHECK: attributes [[ATTR1]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: write) }
diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
index 2f3994df03784..e166c130e3a72 100644
--- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
+++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
@@ -46,6 +46,8 @@ svfloat32_t test_svdot_f32_mf8(svfloat32_t zda, svmfloat8_t
zn, svmfloat8_t zm,
return SVE_ACLE_FUNC(svdot,_f32_mf8,_fpm)(zda, zn, zm, fpm);
}
+// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR1:#.*]]
+
// CHECK-LABEL: define dso_local <vscale x 4 x float> @test_svdot_n_f32_mf8(
// CHECK-SAME: <vscale x 4 x float> [[ZDA:%.*]], <vscale x 16 x i8>
[[ZN:%.*]], <1 x i8> [[ZM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -147,3 +149,6 @@ svfloat32_t test_svdot_lane_f32_mf8(svfloat32_t zda,
svmfloat8_t zn, svmfloat8_t
svfloat16_t test_svdot_lane_f16_mf8(svfloat16_t zda, svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpm) STREAMING {
return SVE_ACLE_FUNC(svdot_lane,_f16_mf8,_fpm)(zda, zn, zm, 7, fpm);
}
+
+
+// CHECK: attributes [[ATTR1]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: write) }
diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
index 425e6a57ffe3c..de5fffc0116d9 100644
--- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
+++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
@@ -46,6 +46,8 @@ svfloat16_t test_svmlalb_f16_mf8(svfloat16_t zda, svmfloat8_t
zn, svmfloat8_t zm
return SVE_ACLE_FUNC(svmlalb,_f16_mf8,_fpm)(zda, zn, zm, fpm);
}
+// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR1:#.*]]
+
// CHECK-LABEL: define dso_local <vscale x 8 x half> @test_svmlalb_n_f16_mf8(
// CHECK-SAME: <vscale x 8 x half> [[ZDA:%.*]], <vscale x 16 x i8> [[ZN:%.*]],
<1 x i8> [[ZM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -387,3 +389,6 @@ svfloat32_t test_svmlalltb_lane_f32_mf8(svfloat32_t zda,
svmfloat8_t zn, svmfloa
svfloat32_t test_svmlalltt_lane_f32_mf8(svfloat32_t zda, svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpm) STREAMING {
return SVE_ACLE_FUNC(svmlalltt_lane,_f32_mf8,_fpm)(zda, zn, zm, 7, fpm);
}
+
+
+// CHECK: attributes [[ATTR1]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: write) }
diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td
b/llvm/include/llvm/IR/IntrinsicsAArch64.td
index 0ec5f5163118e..31d05bc163fa3 100644
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -761,7 +761,7 @@ let TargetPrefix = "aarch64" in {
class RNDR_Intrinsic
: DefaultAttrsIntrinsic<[llvm_i64_ty, llvm_i1_ty], [], [IntrNoMem,
IntrHasSideEffects]>;
class FPMR_Set_Intrinsic
- : DefaultAttrsIntrinsic<[], [llvm_i64_ty], [IntrInaccessibleMemOnly]>;
+ : DefaultAttrsIntrinsic<[], [llvm_i64_ty], [IntrWriteMem,
IntrInaccessibleMemOnly]>;
}
// FP environment registers.
>From a1b75bfe6935e1fce7082b37fdb3b7f32679525d Mon Sep 17 00:00:00 2001
From: CarolineConcatto <caroline.conca...@arm.com>
Date: Thu, 3 Jul 2025 09:38:25 +0000
Subject: [PATCH 2/3] New test file for fp8 to check memory function attribute
---
.../test/CodeGen/AArch64/attr-fp8-function.c | 37 +++++++++++++++++++
.../fp8-intrinsics/acle_neon_fp8_cvt.c | 3 --
.../fp8-intrinsics/acle_neon_fp8_fdot.c | 3 --
.../fp8-intrinsics/acle_neon_fp8_fmla.c | 4 --
.../fp8-intrinsics/acle_sme2_fp8_cvt.c | 3 --
.../fp8-intrinsics/acle_sme2_fp8_fmopa.c | 4 --
.../fp8-intrinsics/acle_sme2_fp8_mla.c | 5 ---
.../fp8-intrinsics/acle_sve2_fp8_cvt.c | 5 ---
.../fp8-intrinsics/acle_sve2_fp8_cvtn.c | 5 ---
.../fp8-intrinsics/acle_sve2_fp8_fdot.c | 5 ---
.../fp8-intrinsics/acle_sve2_fp8_fmla.c | 5 ---
11 files changed, 37 insertions(+), 42 deletions(-)
create mode 100644 clang/test/CodeGen/AArch64/attr-fp8-function.c
diff --git a/clang/test/CodeGen/AArch64/attr-fp8-function.c
b/clang/test/CodeGen/AArch64/attr-fp8-function.c
new file mode 100644
index 0000000000000..54bfd177bd809
--- /dev/null
+++ b/clang/test/CodeGen/AArch64/attr-fp8-function.c
@@ -0,0 +1,37 @@
+// Check memory attribute for FP8 function
+
+// REQUIRES: aarch64-registered-target
+
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon
-target-feature +fp8 -target-feature +sve -target-feature +sme -target-feature
+sme2 -target-feature +sme-f8f16 -target-feature +sme-f8f32 -target-feature
+ssve-fp8fma -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+
+#include <arm_neon.h>
+#include <arm_sme.h>
+
+
+// SIMD
+mfloat8x16_t test_vcvtq_mf8_f16_fpm(float16x8_t vn, float16x8_t vm, fpm_t fpm)
{
+ return vcvtq_mf8_f16_fpm(vn, vm, fpm);
+}
+
+// SVE
+svfloat16_t test_svcvtlt2_f16_mf8(svmfloat8_t zn, fpm_t fpm) __arm_streaming {
+ return svcvtlt2_f16_mf8_fpm(zn, fpm);
+}
+
+// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR3:#.*]]
+// CHECK: declare <vscale x 8 x half>
@llvm.aarch64.sve.fp8.cvtlt2.nxv8f16(<vscale x 16 x i8>) [[ATTR4:#.*]]
+
+
+// SME
+svfloat32_t test_svmlalltt_lane_f32_mf8(svfloat32_t zda, svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpm) __arm_streaming {
+ return svmlalltt_lane_f32_mf8_fpm(zda, zn, zm, 7, fpm);
+}
+
+// CHECK: declare <vscale x 4 x float>
@llvm.aarch64.sve.fp8.fmlalltt.lane.nxv4f32(<vscale x 4 x float>, <vscale x 16
x i8>, <vscale x 16 x i8>, i32 immarg) [[ATTR4]]
+
+// CHECK: declare <16 x i8> @llvm.aarch64.neon.fp8.fcvtn.v16i8.v8f16(<8 x
half>, <8 x half>) [[ATTR4]]
+
+// CHECK: attributes [[ATTR1:#.*]] = {{{.*}}}
+// CHECK: attributes [[ATTR2:#.*]] = {{{.*}}}
+// CHECK: attributes [[ATTR3]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: write) }
+// CHECK: attributes [[ATTR4]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: read) }
diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
index f7030b62c0f8e..9913c54567719 100644
--- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
+++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_cvt.c
@@ -330,6 +330,3 @@ mfloat8x8_t test_vcvt_mf8_f16_fpm(float16x4_t vn,
float16x4_t vm, fpm_t fpm) {
mfloat8x16_t test_vcvtq_mf8_f16_fpm(float16x8_t vn, float16x8_t vm, fpm_t fpm)
{
return vcvtq_mf8_f16_fpm(vn, vm, fpm);
}
-
-// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR1:#.*]]
-// CHECK: attributes [[ATTR1]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: write) }
diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
index c9c4e277440ae..e3cbe425542b0 100644
--- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
+++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
@@ -83,8 +83,6 @@ float16x4_t test_vdot_lane_f16(float16x4_t vd, mfloat8x8_t
vn, mfloat8x8_t vm, f
return vdot_lane_f16_mf8_fpm(vd, vn, vm, 3, fpmr);
}
-// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR1:#.*]]
-
// CHECK-LABEL: define dso_local <4 x half> @test_vdot_laneq_f16(
// CHECK-SAME: <4 x half> noundef [[VD:%.*]], <8 x i8> [[VN:%.*]], <16 x i8>
[[VM:%.*]], i64 noundef [[FPMR:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -271,4 +269,3 @@ float32x4_t test_vdotq_laneq_f32(float32x4_t vd,
mfloat8x16_t vn, mfloat8x16_t v
return vdotq_laneq_f32_mf8_fpm(vd, vn, vm, 3, fpmr);
}
-// CHECK: attributes [[ATTR1]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: write) }
diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
index 222a8e7272745..d4f074a92b05b 100644
--- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
+++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fmla.c
@@ -154,8 +154,6 @@ float16x8_t test_vmlalb_lane(float16x8_t vd, mfloat8x16_t
vn, mfloat8x8_t vm, fp
return vmlalbq_lane_f16_mf8_fpm(vd, vn, vm, 0, fpm);
}
-// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR1:#.*]]
-
// CHECK-LABEL: define dso_local <8 x half> @test_vmlalb_laneq(
// CHECK-SAME: <8 x half> noundef [[VD:%.*]], <16 x i8> [[VN:%.*]], <16 x i8>
[[VM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -381,5 +379,3 @@ float32x4_t test_vmlalltt_lane(float32x4_t vd, mfloat8x16_t
vn, mfloat8x8_t vm,
float32x4_t test_vmlalltt_laneq(float32x4_t vd, mfloat8x16_t vn, mfloat8x16_t
vm, fpm_t fpm) {
return vmlallttq_laneq_f32_mf8_fpm(vd, vn, vm, 15, fpm);
}
-
-// CHECK: attributes [[ATTR1]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: write) }
diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
index 3dbeb0aab6e25..282445a96f369 100644
--- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
+++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
@@ -32,8 +32,6 @@ svmfloat8_t test_cvt_f16_x2(svfloat16x2_t zn, fpm_t fpmr)
__arm_streaming {
return SVE_ACLE_FUNC(svcvt_mf8,_f16_x2,_fpm)(zn, fpmr);
}
-// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR1:#.*]]
-
// CHECK-LABEL: @test_cvt_f32_x4(
// CHECK-NEXT: entry:
// CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR:%.*]])
@@ -210,4 +208,3 @@ svbfloat16x2_t test_cvtl2_bf16_x2(svmfloat8_t zn, fpm_t
fpmr) __arm_streaming {
return SVE_ACLE_FUNC(svcvtl2_bf16,_mf8,_x2_fpm)(zn, fpmr);
}
-// CHECK: attributes [[ATTR1]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: write) }
diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
index c11baf60c6b48..c4dda5085b3a9 100644
--- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
+++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
@@ -35,8 +35,6 @@ void test_svmopa_za16_mf8_m(svbool_t pn, svbool_t pm,
svmfloat8_t zn,
SVE_ACLE_FUNC(svmopa_za16,_mf8,_m_fpm)(1, pn, pm, zn, zm, fpmr);
}
-// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR1:#.*]]
-//
// CHECK-LABEL: define dso_local void @test_svmopa_za32_mf8_m(
// CHECK-SAME: <vscale x 16 x i1> [[PN:%.*]], <vscale x 16 x i1> [[PM:%.*]],
<vscale x 16 x i8> [[ZN:%.*]], <vscale x 16 x i8> [[ZM:%.*]], i64 noundef
[[FPMR:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -56,5 +54,3 @@ void test_svmopa_za32_mf8_m(svbool_t pn, svbool_t pm,
svmfloat8_t zn,
SVE_ACLE_FUNC(svmopa_za32,_mf8,_m_fpm)(3, pn, pm, zn, zm, fpmr);
}
-
-// CHECK: attributes [[ATTR1]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: write) }
diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
index ef8319ffa6372..d603045edf282 100644
--- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
+++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_mla.c
@@ -35,8 +35,6 @@ void test_svmla_lane_za16_vg2x1(uint32_t slice, svmfloat8_t
zn, svmfloat8_t zm,
SME_ACLE_FUNC(svmla_lane_za16,_mf8,_vg2x1_fpm,,)(slice, zn, zm, 0, fpm);
}
-// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR1:#.*]]
-
// CHECK-LABEL: define dso_local void @test_svmla_lane_za16_vg2x2(
// CHECK-SAME: i32 noundef [[SLICE:%.*]], <vscale x 16 x i8>
[[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8>
[[ZM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -316,6 +314,3 @@ void test_svmla_multi_za32_vg4x2(uint32_t slice,
svmfloat8x2_t zn, svmfloat8x2_t
void test_svmla_multi_za32_vg4x4(uint32_t slice, svmfloat8x4_t zn,
svmfloat8x4_t zm, fpm_t fpm) __arm_streaming __arm_inout("za") {
SME_ACLE_FUNC(svmla_za32,_mf8,_vg4x4_fpm,,)(slice, zn, zm, fpm);
}
-
-
-// CHECK: attributes [[ATTR1]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: write) }
diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
index 7187831f2a0a4..c026b8aa216f3 100644
--- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
+++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvt.c
@@ -46,8 +46,6 @@ svbfloat16_t test_svcvt1_bf16_mf8(svmfloat8_t zn, fpm_t fpm)
STREAMING {
return SVE_ACLE_FUNC(svcvt1_bf16,_mf8,_fpm)(zn, fpm);
}
-// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR1:#.*]]
-
// CHECK-LABEL: define dso_local <vscale x 8 x bfloat> @test_svcvt2_bf16_mf8(
// CHECK-SAME: <vscale x 16 x i8> [[ZN:%.*]], i64 noundef [[FPM:%.*]])
#[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -173,6 +171,3 @@ svfloat16_t test_svcvtlt1_f16_mf8(svmfloat8_t zn, fpm_t
fpm) STREAMING {
svfloat16_t test_svcvtlt2_f16_mf8(svmfloat8_t zn, fpm_t fpm) STREAMING {
return SVE_ACLE_FUNC(svcvtlt2_f16,_mf8,_fpm)(zn, fpm);
}
-
-
-// CHECK: attributes [[ATTR1]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: write) }
diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
index 0ffad95720954..ed5b0ce02af4b 100644
--- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
+++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_cvtn.c
@@ -46,8 +46,6 @@ svmfloat8_t test_svcvtn_f8_bf16(svbfloat16x2_t zn_zm, fpm_t
fpm) STREAMING {
return SVE_ACLE_FUNC(svcvtn_mf8,_bf16_x2,_fpm)(zn_zm, fpm);
}
-// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR1:#.*]]
-
// CHECK-LABEL: define dso_local <vscale x 16 x i8> @test_svcvtn_f8_f16(
// CHECK-SAME: <vscale x 8 x half> [[ZN_ZM_COERCE0:%.*]], <vscale x 8 x half>
[[ZN_ZM_COERCE1:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -101,6 +99,3 @@ svmfloat8_t test_svcvtnb_f8_f32(svfloat32x2_t zn_zm, fpm_t
fpm) STREAMING {
svmfloat8_t test_svcvtnt_f8_f32(svmfloat8_t zd, svfloat32x2_t zn_zm, fpm_t
fpm) STREAMING {
return SVE_ACLE_FUNC(svcvtnt_mf8,_f32_x2,_fpm)(zd, zn_zm, fpm);
}
-
-
-// CHECK: attributes [[ATTR1]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: write) }
diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
index e166c130e3a72..2f3994df03784 100644
--- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
+++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fdot.c
@@ -46,8 +46,6 @@ svfloat32_t test_svdot_f32_mf8(svfloat32_t zda, svmfloat8_t
zn, svmfloat8_t zm,
return SVE_ACLE_FUNC(svdot,_f32_mf8,_fpm)(zda, zn, zm, fpm);
}
-// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR1:#.*]]
-
// CHECK-LABEL: define dso_local <vscale x 4 x float> @test_svdot_n_f32_mf8(
// CHECK-SAME: <vscale x 4 x float> [[ZDA:%.*]], <vscale x 16 x i8>
[[ZN:%.*]], <1 x i8> [[ZM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -149,6 +147,3 @@ svfloat32_t test_svdot_lane_f32_mf8(svfloat32_t zda,
svmfloat8_t zn, svmfloat8_t
svfloat16_t test_svdot_lane_f16_mf8(svfloat16_t zda, svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpm) STREAMING {
return SVE_ACLE_FUNC(svdot_lane,_f16_mf8,_fpm)(zda, zn, zm, 7, fpm);
}
-
-
-// CHECK: attributes [[ATTR1]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: write) }
diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
index de5fffc0116d9..425e6a57ffe3c 100644
--- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
+++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sve2_fp8_fmla.c
@@ -46,8 +46,6 @@ svfloat16_t test_svmlalb_f16_mf8(svfloat16_t zda, svmfloat8_t
zn, svmfloat8_t zm
return SVE_ACLE_FUNC(svmlalb,_f16_mf8,_fpm)(zda, zn, zm, fpm);
}
-// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR1:#.*]]
-
// CHECK-LABEL: define dso_local <vscale x 8 x half> @test_svmlalb_n_f16_mf8(
// CHECK-SAME: <vscale x 8 x half> [[ZDA:%.*]], <vscale x 16 x i8> [[ZN:%.*]],
<1 x i8> [[ZM:%.*]], i64 noundef [[FPM:%.*]]) #[[ATTR0]] {
// CHECK-NEXT: [[ENTRY:.*:]]
@@ -389,6 +387,3 @@ svfloat32_t test_svmlalltb_lane_f32_mf8(svfloat32_t zda,
svmfloat8_t zn, svmfloa
svfloat32_t test_svmlalltt_lane_f32_mf8(svfloat32_t zda, svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpm) STREAMING {
return SVE_ACLE_FUNC(svmlalltt_lane,_f32_mf8,_fpm)(zda, zn, zm, 7, fpm);
}
-
-
-// CHECK: attributes [[ATTR1]] = { nocallback nofree nosync nounwind
willreturn memory(inaccessiblemem: write) }
>From 9a29cb4cc513eac77aad3100dfb304c9f08737fa Mon Sep 17 00:00:00 2001
From: CarolineConcatto <caroline.conca...@arm.com>
Date: Thu, 3 Jul 2025 09:52:08 +0000
Subject: [PATCH 3/3] [NFC]Remove new line from previous changed files
---
clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c | 1 -
clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c | 1 -
clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c | 1 -
3 files changed, 3 deletions(-)
diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
index e3cbe425542b0..44db59df6c1c4 100644
--- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
+++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_neon_fp8_fdot.c
@@ -268,4 +268,3 @@ float32x4_t test_vdotq_lane_f32(float32x4_t vd,
mfloat8x16_t vn, mfloat8x8_t vm,
float32x4_t test_vdotq_laneq_f32(float32x4_t vd, mfloat8x16_t vn, mfloat8x16_t
vm, fpm_t fpmr) {
return vdotq_laneq_f32_mf8_fpm(vd, vn, vm, 3, fpmr);
}
-
diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
index 282445a96f369..ae2e780f84cfe 100644
--- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
+++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_cvt.c
@@ -207,4 +207,3 @@ svbfloat16x2_t test_cvtl1_bf16_x2(svmfloat8_t zn, fpm_t
fpmr) __arm_streaming {
svbfloat16x2_t test_cvtl2_bf16_x2(svmfloat8_t zn, fpm_t fpmr) __arm_streaming
{
return SVE_ACLE_FUNC(svcvtl2_bf16,_mf8,_x2_fpm)(zn, fpmr);
}
-
diff --git a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
index c4dda5085b3a9..95d6383ab30ef 100644
--- a/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
+++ b/clang/test/CodeGen/AArch64/fp8-intrinsics/acle_sme2_fp8_fmopa.c
@@ -53,4 +53,3 @@ void test_svmopa_za32_mf8_m(svbool_t pn, svbool_t pm,
svmfloat8_t zn,
svmfloat8_t zm, fpm_t fpmr) __arm_streaming
__arm_inout("za") {
SVE_ACLE_FUNC(svmopa_za32,_mf8,_m_fpm)(3, pn, pm, zn, zm, fpmr);
}
-
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
