https://github.com/BoyaoWang430 updated https://github.com/llvm/llvm-project/pull/127463
>From aea8133a1fe38791bad4a45e6dcc53d9fe05f771 Mon Sep 17 00:00:00 2001 From: wangboyao <wangbo...@bytedance.com> Date: Thu, 3 Jul 2025 16:08:15 +0800 Subject: [PATCH] [RISCV][MC] Add MC support of Zibi experimental extension This adds the MC support of Zibi v0.1 experimental extension. References: https://lf-riscv.atlassian.net/wiki/spaces/USXX/pages/599261201/Branch+with+Immediate+Zibi+Ratification+Plan https://lf-riscv.atlassian.net/browse/RVS-3828 --- .../Driver/print-supported-extensions-riscv.c | 1 + .../test/Preprocessor/riscv-target-features.c | 9 +++ llvm/docs/RISCVUsage.rst | 3 + llvm/docs/ReleaseNotes.md | 2 + .../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 9 +++ .../RISCV/Disassembler/RISCVDisassembler.cpp | 8 +++ .../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 1 + .../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 17 +++++ llvm/lib/Target/RISCV/RISCVFeatures.td | 6 ++ llvm/lib/Target/RISCV/RISCVInstrFormats.td | 16 +++++ llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 + llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td | 42 +++++++++++++ llvm/test/CodeGen/RISCV/attributes.ll | 4 ++ llvm/test/CodeGen/RISCV/features-info.ll | 1 + llvm/test/MC/RISCV/zibi-invalid.s | 34 ++++++++++ llvm/test/MC/RISCV/zibi-valid.s | 63 +++++++++++++++++++ .../TargetParser/RISCVISAInfoTest.cpp | 1 + 17 files changed, 218 insertions(+) create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td create mode 100644 llvm/test/MC/RISCV/zibi-invalid.s create mode 100644 llvm/test/MC/RISCV/zibi-valid.s diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 314fdad7e52e7..a703948316298 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -205,6 +205,7 @@ // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions // CHECK-NEXT: p 0.14 'P' ('Base P' (Packed SIMD)) +// CHECK-NEXT: zibi 0.1 'Zibi' (Branch with Immediate) // CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad) // CHECK-NEXT: zicfiss 1.0 'Zicfiss' (Shadow stack) // CHECK-NEXT: zalasr 0.1 'Zalasr' (Load-Acquire and Store-Release Instructions) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 86085c21a95aa..52a483100f829 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -122,6 +122,7 @@ // CHECK-NOT: __riscv_zfinx {{.*$}} // CHECK-NOT: __riscv_zhinx {{.*$}} // CHECK-NOT: __riscv_zhinxmin {{.*$}} +// CHECK-NOT: __riscv_zibi {{.*$}} // CHECK-NOT: __riscv_zic64b {{.*$}} // CHECK-NOT: __riscv_zicbom {{.*$}} // CHECK-NOT: __riscv_zicbop {{.*$}} @@ -1029,6 +1030,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZHINXMIN-EXT %s // CHECK-ZHINXMIN-EXT: __riscv_zhinxmin 1000000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zibi0p1 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZIBI-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zibi0p1 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZIBI-EXT %s +// CHECK-ZIBI-EXT: __riscv_zibi + // RUN: %clang --target=riscv32-unknown-linux-gnu \ // RUN: -march=rv32izic64b -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZIC64B-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 81684ba30f12c..b04f65974b0d0 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -326,6 +326,9 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-zalasr`` LLVM implements the `0.0.5 draft specification <https://github.com/mehnadnerd/riscv-zalasr>`__. +``experimental-zibi`` + LLVM implements the `0.1 release specification <https://lf-riscv.atlassian.net/wiki/spaces/USXX/pages/599261201/Branch+with+Immediate+Zibi+Ratification+Plan>`__. + ``experimental-zicfilp``, ``experimental-zicfiss`` LLVM implements the `1.0 release specification <https://github.com/riscv/riscv-cfi/releases/tag/v1.0>`__. diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 26384d94d04fc..7bb4138b288b2 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -177,6 +177,8 @@ Changes to the RISC-V Backend extension. * Adds experimental assembler support for the Qualcomm uC 'Xqciio` (External Input Output) extension. +* Adds experimental assembler and code generation support for the 'Zibi` (Branch with Immediate) + extension. * Adds assembler support for the 'Zilsd` (Load/Store Pair Instructions) extension. * Adds assembler support for the 'Zclsd` (Compressed Load/Store Pair Instructions) diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index bb0f9df2032fd..f239bdfbb208a 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -744,6 +744,11 @@ struct RISCVOperand final : public MCParsedAsmOperand { return isUImmPred([](int64_t Imm) { return Imm != 0 && isUInt<5>(Imm); }); } + bool isUImm5Zibi() const { + return isUImmPred( + [](int64_t Imm) { return (Imm != 0 && isUInt<5>(Imm)) || Imm == -1; }); + } + bool isUImm5GT3() const { return isUImmPred([](int64_t Imm) { return isUInt<5>(Imm) && Imm > 3; }); } @@ -1470,6 +1475,10 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1); case Match_InvalidUImm5NonZero: return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5) - 1); + case Match_InvalidUImm5Zibi: + return generateImmOutOfRangeError( + Operands, ErrorInfo, -1, (1 << 5) - 1, + "immediate must be non-zero in the range"); case Match_InvalidUImm5GT3: return generateImmOutOfRangeError(Operands, ErrorInfo, 4, (1 << 5) - 1); case Match_InvalidUImm5Plus1: diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 52061e96d0018..72c3415d3ea2e 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -457,6 +457,14 @@ static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm, return decodeUImmOperand<N>(Inst, Imm, Address, Decoder); } +static DecodeStatus decodeUImmZibiOperand(MCInst &Inst, uint32_t Imm, + int64_t Address, + const MCDisassembler *Decoder) { + assert(isUInt<5>(Imm) && "Invalid immediate"); + Inst.addOperand(MCOperand::createImm(Imm ? Imm : -1LL)); + return MCDisassembler::Success; +} + static DecodeStatus decodeUImmLog2XLenNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address, const MCDisassembler *Decoder) { diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h index d296f76ad10ca..96733ea2d40a6 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -301,6 +301,7 @@ enum OperandType : unsigned { OPERAND_UIMM4, OPERAND_UIMM5, OPERAND_UIMM5_NONZERO, + OPERAND_UIMM5_ZIBI, OPERAND_UIMM5_GT3, OPERAND_UIMM5_PLUS1, OPERAND_UIMM5_GE6_PLUS1, diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp index ce0fbc0ac0654..d6fd6a9323dd4 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp @@ -97,6 +97,10 @@ class RISCVMCCodeEmitter : public MCCodeEmitter { SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const; + uint64_t getImmOpValueZibi(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const; + uint64_t getImmOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const; @@ -545,6 +549,19 @@ RISCVMCCodeEmitter::getImmOpValueAsrN(const MCInst &MI, unsigned OpNo, return getImmOpValue(MI, OpNo, Fixups, STI); } +uint64_t +RISCVMCCodeEmitter::getImmOpValueZibi(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpNo); + assert(MO.isImm() && "Zibi operand must be an immediate"); + int64_t Res = MO.getImm(); + if (Res == -1) + return 0; + + return Res; +} + uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const { diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 6e103dd7d8c44..fafb50ded37aa 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -78,6 +78,12 @@ def FeatureStdExtE : RISCVExtension<2, 0, "Embedded Instruction Set with 16 GPRs">, RISCVExtensionBitmask<0, 4>; +def FeatureStdExtZibi + : RISCVExperimentalExtension<0, 1, "Branch with Immediate">; +def HasStdExtZibi : Predicate<"Subtarget->hasStdExtZibi()">, + AssemblerPredicate<(all_of FeatureStdExtZibi), + "'Zibi' (Branch with Immediate)">; + def FeatureStdExtZic64b : RISCVExtension<1, 0, "Cache Block Size Is 64 Bytes">; diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td index b6b64b57b1b3e..19de5a0ac4005 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td +++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td @@ -496,6 +496,22 @@ class RVInstB<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins, let Inst{6-0} = opcode.Value; } +class RVInstBIMM<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins, + string opcodestr, string argstr> + : RVInst<outs, ins, opcodestr, argstr, [], InstFormatB> { + bits<12> imm12; + bits<5> cimm; + bits<5> rs1; + let Inst{31} = imm12{11}; + let Inst{30-25} = imm12{9-4}; + let Inst{24-20} = cimm; + let Inst{19-15} = rs1; + let Inst{14-12} = funct3; + let Inst{11-8} = imm12{3-0}; + let Inst{7} = imm12{10}; + let Inst{6-0} = opcode.Value; +} + class RVInstU<RISCVOpcode opcode, dag outs, dag ins, string opcodestr, string argstr> : RVInst<outs, ins, opcodestr, argstr, [], InstFormatU> { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index e0321443ba2d4..40ea3301adccf 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -2255,6 +2255,7 @@ include "RISCVInstrInfoZicbo.td" include "RISCVInstrInfoZicond.td" include "RISCVInstrInfoZicfiss.td" include "RISCVInstrInfoZilsd.td" +include "RISCVInstrInfoZibi.td" // Scalar FP include "RISCVInstrInfoF.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td new file mode 100644 index 0000000000000..cec15cb2d5469 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td @@ -0,0 +1,42 @@ +//===-- RISCVInstrInfoZibi.td - 'Zibi' instructions ------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// This file describes the RISC-V instructions for 'Zibi' (branch with imm). +/// +//===----------------------------------------------------------------------===// +// A 5-bit unsigned immediate representing 1-31 and -1. 00000 represents -1. +def uimm5_zibi : RISCVOp<XLenVT>, ImmLeaf<XLenVT, [{ + return (Imm != 0 && isUInt<5>(Imm)) || Imm == -1; +}]> { + let ParserMatchClass = UImmAsmOperand<5, "Zibi">; + let EncoderMethod = "getImmOpValueZibi"; + let DecoderMethod = "decodeUImmZibiOperand"; + let MCOperandPredicate = [{ + int64_t Imm; + if (!MCOp.evaluateAsConstantImm(Imm)) + return false; + return (Imm >= 1 && Imm <= 31) || Imm == -1; + }]; + let OperandType = "OPERAND_UIMM5_ZIBI"; +} + +class Branch_imm<bits<3> funct3, string opcodestr> + : RVInstBIMM<funct3, OPC_BRANCH, (outs), + (ins GPR:$rs1, uimm5_zibi:$cimm, bare_simm13_lsb0:$imm12), + opcodestr, "$rs1, $cimm, $imm12">, + Sched<[WriteJmp, ReadJmp]> { + let isBranch = 1; + let isTerminator = 1; + let hasSideEffects = 0; + let mayLoad = 0; + let mayStore = 0; +} +let Predicates = [HasStdExtZibi] in { + def BEQI : Branch_imm<0b010, "beqi">; + def BNEI : Branch_imm<0b011, "bnei">; +} // Predicates = [HasStdExtZibi] \ No newline at end of file diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index d0afea9754aa0..e3e170fcbcb10 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -173,6 +173,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+supm %s -o - | FileCheck --check-prefix=RV32SUPM %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV32SMCTR %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV32SSCTR %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zibi %s -o - | FileCheck --check-prefix=RV32ZIBI %s ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s @@ -338,6 +339,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-xqccmp %s -o - | FileCheck --check-prefix=RV64XQCCMP %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-p %s -o - | FileCheck --check-prefix=RV64P %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zibi %s -o - | FileCheck --check-prefix=RV64ZIBI %s ; Tests for profile features. @@ -528,6 +530,7 @@ ; RV32SMCTR: .attribute 5, "rv32i2p1_smctr1p0_sscsrind1p0" ; RV32SSCTR: .attribute 5, "rv32i2p1_sscsrind1p0_ssctr1p0" ; RV32P: .attribute 5, "rv32i2p1_p0p14" +; RV32ZIBI: .attribute 5, "rv32i2p1_zibi0p1" ; RV64M: .attribute 5, "rv64i2p1_m2p0_zmmul1p0" ; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0" @@ -691,6 +694,7 @@ ; RV64SDTRIG: .attribute 5, "rv64i2p1_sdtrig1p0" ; RV64XQCCMP: .attribute 5, "rv64i2p1_zca1p0_xqccmp0p3" ; RV64P: .attribute 5, "rv64i2p1_p0p14" +; RV64ZIBI: .attribute 5, "rv64i2p1_zibi0p1" ; RVI20U32: .attribute 5, "rv32i2p1" ; RVI20U64: .attribute 5, "rv64i2p1" diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index af2e31e5d5331..dff785177b43d 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -46,6 +46,7 @@ ; CHECK-NEXT: experimental-xsfmclic - 'XSfmclic' (SiFive CLIC Machine-mode CSRs). ; CHECK-NEXT: experimental-xsfsclic - 'XSfsclic' (SiFive CLIC Supervisor-mode CSRs). ; CHECK-NEXT: experimental-zalasr - 'Zalasr' (Load-Acquire and Store-Release Instructions). +; CHECK-NEXT: experimental-zibi - 'Zibi' (Branch with Immediate). ; CHECK-NEXT: experimental-zicfilp - 'Zicfilp' (Landing pad). ; CHECK-NEXT: experimental-zicfiss - 'Zicfiss' (Shadow stack). ; CHECK-NEXT: experimental-zvbc32e - 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements). diff --git a/llvm/test/MC/RISCV/zibi-invalid.s b/llvm/test/MC/RISCV/zibi-invalid.s new file mode 100644 index 0000000000000..4c725ef52ca0b --- /dev/null +++ b/llvm/test/MC/RISCV/zibi-invalid.s @@ -0,0 +1,34 @@ +# RUN: not llvm-mc -triple=riscv32 --mattr=+experimental-zibi %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: not llvm-mc -triple=riscv64 --mattr=+experimental-zibi %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +beqi a0, 0x0, 0x400 +# CHECK-ERROR: [[@LINE-1]]:10: error: immediate must be non-zero in the range [-1, 31] +# CHECK-ERROR-LABEL: beqi a0, 0x0, 0x400 +beqi a0, 0x21, 0x400 +# CHECK-ERROR: [[@LINE-1]]:10: error: immediate must be non-zero in the range [-1, 31] +# CHECK-ERROR-LABEL: beqi a0, 0x21, 0x400 +beqi a2, 0x10, -0x1f000 +# CHECK-ERROR: [[@LINE-1]]:16: error: immediate must be a multiple of 2 bytes in the range [-4096, 4094] +# CHECK-ERROR-LABEL: beqi a2, 0x10, -0x1f000 +beqi a2, 0x10, 0x1000 +# CHECK-ERROR: [[@LINE-1]]:16: error: immediate must be a multiple of 2 bytes in the range [-4096, 4094] +# CHECK-ERROR-LABEL: beqi a2, 0x10, 0x1000 +beqi a2, 0x10, 0x111 +# CHECK-ERROR: [[@LINE-1]]:16: error: immediate must be a multiple of 2 bytes in the range [-4096, 4094] +# CHECK-ERROR-LABEL: beqi a2, 0x10, 0x111 +bnei a0, 0x0, 0x400 +# CHECK-ERROR: [[@LINE-1]]:10: error: immediate must be non-zero in the range [-1, 31] +# CHECK-ERROR-LABEL: bnei a0, 0x0, 0x400 +bnei a0, 0x21, 0x400 +# CHECK-ERROR: [[@LINE-1]]:10: error: immediate must be non-zero in the range [-1, 31] +# CHECK-ERROR-LABEL: bnei a0, 0x21, 0x400 +bnei a2, 0x10, -0x1f000 +# CHECK-ERROR: [[@LINE-1]]:16: error: immediate must be a multiple of 2 bytes in the range [-4096, 4094] +# CHECK-ERROR-LABEL: bnei a2, 0x10, -0x1f000 +bnei a2, 0x10, 0x1000 +# CHECK-ERROR: [[@LINE-1]]:16: error: immediate must be a multiple of 2 bytes in the range [-4096, 4094] +# CHECK-ERROR-LABEL: bnei a2, 0x10, 0x1000 +bnei a2, 0x10, 0x111 +# CHECK-ERROR: [[@LINE-1]]:16: error: immediate must be a multiple of 2 bytes in the range [-4096, 4094] +# CHECK-ERROR-LABEL: bnei a2, 0x10, 0x111 \ No newline at end of file diff --git a/llvm/test/MC/RISCV/zibi-valid.s b/llvm/test/MC/RISCV/zibi-valid.s new file mode 100644 index 0000000000000..b062c4cf1efb3 --- /dev/null +++ b/llvm/test/MC/RISCV/zibi-valid.s @@ -0,0 +1,63 @@ +# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+experimental-zibi %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-ASM +# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zibi %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-ASM +# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zibi %s \ +# RUN: | llvm-objdump -d --mattr=+experimental-zibi --no-print-imm-hex - \ +# RUN: | FileCheck %s --check-prefix=CHECK-OBJ +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+experimental-zibi %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zibi %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +beqi a0, 1, 1024 +# CHECK-OBJ: beqi a0, 1, 0x400 +# CHECK-ASM: beqi a0, 1, 1024 +# CHECK-ENCODING: [0x63,0x20,0x15,0x40] +# CHECK-ERROR: instruction requires the following: 'Zibi' (Branch with Immediate){{$}} +# CHECK-UNKNOWN: 40152063 <unknown> +beqi a5, -1, -1024 +# CHECK-OBJ: beqi a5, -1, 0xfffffc04 +# CHECK-ASM: beqi a5, -1, -1024 +# CHECK-ENCODING: [0xe3,0xa0,0x07,0xc0] +# CHECK-ERROR: instruction requires the following: 'Zibi' (Branch with Immediate){{$}} +# CHECK-UNKNOWN: c007a0e3 <unknown> +beqi s0, 22, 0xffe +# CHECK-OBJ: beqi s0, 22, 0x1006 +# CHECK-ASM: beqi s0, 22, 4094 +# CHECK-ENCODING: [0xe3,0x2f,0x64,0x7f] +# CHECK-ERROR: instruction requires the following: 'Zibi' (Branch with Immediate){{$}} +# CHECK-UNKNOWN: 7f642fe3 <unknown> +beqi s1, 11, -4096 +# CHECK-OBJ: beqi s1, 11, 0xfffff00c +# CHECK-ASM: beqi s1, 11, -4096 +# CHECK-ENCODING: [0x63,0xa0,0xb4,0x80] +# CHECK-ERROR: instruction requires the following: 'Zibi' (Branch with Immediate){{$}} +# CHECK-UNKNOWN: 80b4a063 <unknown> +bnei a0, 1, 1024 +# CHECK-OBJ: bnei a0, 1, 0x410 +# CHECK-ASM: bnei a0, 1, 1024 +# CHECK-ENCODING: [0x63,0x30,0x15,0x40] +# CHECK-ERROR: instruction requires the following: 'Zibi' (Branch with Immediate){{$}} +# CHECK-UNKNOWN: 40153063 <unknown> +bnei a5, -1, -1024 +# CHECK-OBJ: bnei a5, -1, 0xfffffc14 +# CHECK-ASM: bnei a5, -1, -1024 +# CHECK-ENCODING: [0xe3,0xb0,0x07,0xc0] +# CHECK-ERROR: instruction requires the following: 'Zibi' (Branch with Immediate){{$}} +# CHECK-UNKNOWN: c007b0e3 <unknown> +bnei s0, 22, 0xffe +# CHECK-OBJ: bnei s0, 22, 0x1016 +# CHECK-ASM: bnei s0, 22, 4094 +# CHECK-ENCODING: [0xe3,0x3f,0x64,0x7f] +# CHECK-ERROR: instruction requires the following: 'Zibi' (Branch with Immediate){{$}} +# CHECK-UNKNOWN: 7f643fe3 <unknown> +bnei s1, 11, -4096 +# CHECK-OBJ: bnei s1, 11, 0xfffff01c +# CHECK-ASM: bnei s1, 11, -4096 +# CHECK-ENCODING: [0x63,0xb0,0xb4,0x80] +# CHECK-ERROR: instruction requires the following: 'Zibi' (Branch with Immediate){{$}} +# CHECK-UNKNOWN: 80b4b063 <unknown> diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 66e335a33a3f7..2d31046eb1928 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1176,6 +1176,7 @@ R"(All available -march extensions for RISC-V Experimental extensions p 0.14 + zibi 0.1 zicfilp 1.0 This is a long dummy description zicfiss 1.0 zalasr 0.1 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
