llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-aarch64 Author: Paul Walker (paulwalker-arm) <details> <summary>Changes</summary> Adds sve-sha3 to reference FEAT_SVE_SHA3 without specifically enabling SVE2. The SVE2 requirement for AES, SHA3 and Bitperm is replaced with SVE for non-streaming function. --- Patch is 49.41 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/145696.diff 37 Files Affected: - (modified) clang/test/CodeGen/AArch64/fmv-dependencies.c (+1-1) - (modified) clang/test/Driver/aarch64-implied-sve-features.c (+2-2) - (modified) clang/test/Driver/print-enabled-extensions/aarch64-fujitsu-monaka.c (+1-1) - (modified) clang/test/Driver/print-enabled-extensions/aarch64-grace.c (+1-1) - (modified) clang/test/Driver/print-enabled-extensions/aarch64-olympus.c (+1-1) - (modified) clang/test/Driver/print-supported-extensions-aarch64.c (+2-1) - (modified) llvm/lib/Target/AArch64/AArch64.td (+3-3) - (modified) llvm/lib/Target/AArch64/AArch64Features.td (+5-2) - (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.td (+17-12) - (modified) llvm/lib/Target/AArch64/AArch64Processors.td (+3-3) - (modified) llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td (+5-5) - (modified) llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (+2-1) - (modified) llvm/lib/TargetParser/AArch64TargetParser.cpp (+7) - (modified) llvm/test/CodeGen/AArch64/sve2-intrinsics-bit-permutation.ll (+4-1) - (modified) llvm/test/CodeGen/AArch64/sve2-intrinsics-crypto.ll (+3-1) - (modified) llvm/test/CodeGen/AArch64/sve2-intrinsics-rax1.ll (+2) - (modified) llvm/test/MC/AArch64/SME2p1/directive-arch_extension-negative.s (+1-1) - (modified) llvm/test/MC/AArch64/SVE2/aesd.s (+1-1) - (modified) llvm/test/MC/AArch64/SVE2/aese.s (+1-1) - (modified) llvm/test/MC/AArch64/SVE2/aesimc.s (+2-2) - (modified) llvm/test/MC/AArch64/SVE2/aesmc.s (+2-2) - (modified) llvm/test/MC/AArch64/SVE2/bdep.s (+4-4) - (modified) llvm/test/MC/AArch64/SVE2/bext.s (+4-4) - (modified) llvm/test/MC/AArch64/SVE2/bgrp.s (+4-4) - (modified) llvm/test/MC/AArch64/SVE2/directive-arch-negative.s (+1-1) - (modified) llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s (+3-9) - (modified) llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s (+3-3) - (modified) llvm/test/MC/AArch64/SVE2/pmullb-128.s (+1-1) - (modified) llvm/test/MC/AArch64/SVE2/pmullt-128.s (+1-1) - (modified) llvm/test/MC/AArch64/SVE2/rax1.s (+5-1) - (modified) llvm/test/MC/AArch64/SVE2p1/aesd.s (+6-6) - (modified) llvm/test/MC/AArch64/SVE2p1/aesdimc.s (+6-6) - (modified) llvm/test/MC/AArch64/SVE2p1/aese.s (+6-6) - (modified) llvm/test/MC/AArch64/SVE2p1/aesemc.s (+6-6) - (modified) llvm/test/MC/AArch64/SVE2p1/pmlal.s (+3-3) - (modified) llvm/test/MC/AArch64/SVE2p1/pmull.s (+3-3) - (modified) llvm/unittests/TargetParser/TargetParserTest.cpp (+9-1) ``````````diff diff --git a/clang/test/CodeGen/AArch64/fmv-dependencies.c b/clang/test/CodeGen/AArch64/fmv-dependencies.c index 7aaf143f2afc5..a97c4e95cd032 100644 --- a/clang/test/CodeGen/AArch64/fmv-dependencies.c +++ b/clang/test/CodeGen/AArch64/fmv-dependencies.c @@ -188,7 +188,7 @@ int caller() { // CHECK: attributes #[[sve2]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve2,+v8a" // CHECK: attributes #[[sve2_aes]] = { {{.*}} "target-features"="+aes,+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve-aes,+sve2,+sve2-aes,+v8a" // CHECK: attributes #[[sve2_bitperm]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sve,+sve-bitperm,+sve2,+sve2-bitperm,+v8a" -// CHECK: attributes #[[sve2_sha3]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sha2,+sha3,+sve,+sve2,+sve2-sha3,+v8a" +// CHECK: attributes #[[sve2_sha3]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sha2,+sha3,+sve,+sve-sha3,+sve2,+sve2-sha3,+v8a" // CHECK: attributes #[[sve2_sm4]] = { {{.*}} "target-features"="+fp-armv8,+fullfp16,+neon,+outline-atomics,+sm4,+sve,+sve2,+sve2-sm4,+v8a" // CHECK: attributes #[[wfxt]] = { {{.*}} "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a,+wfxt" // CHECK: attributes #[[cssc]] = { {{.*}} "target-features"="+cssc,+fp-armv8,+neon,+outline-atomics,+v8a" diff --git a/clang/test/Driver/aarch64-implied-sve-features.c b/clang/test/Driver/aarch64-implied-sve-features.c index ecc1e9500b667..18c39974a5c14 100644 --- a/clang/test/Driver/aarch64-implied-sve-features.c +++ b/clang/test/Driver/aarch64-implied-sve-features.c @@ -46,13 +46,13 @@ // SVE2-AES-REVERT: "-target-feature" "+sve" "-target-feature" "-sve-aes" "-target-feature" "+sve2" "-target-feature" "-sve2-aes" // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sha3+nosve2-sha3 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SHA3-REVERT -// SVE2-SHA3-REVERT: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "-sve2-sha3" +// SVE2-SHA3-REVERT: "-target-feature" "+sve" "-target-feature" "-sve-sha3" "-target-feature" "+sve2" "-target-feature" "-sve2-sha3" // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sm4+nosve2-sm4 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SM4-REVERT // SVE2-SM4-REVERT: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "-sve2-sm4" // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve2-sha3 %s -### 2>&1 | FileCheck %s --check-prefix=SVE2-SHA3 -// SVE2-SHA3: "-target-feature" "+sve" "-target-feature" "+sve2" "-target-feature" "+sve2-sha3" +// SVE2-SHA3: "-target-feature" "+sve" "-target-feature" "+sve-sha3" "-target-feature" "+sve2" "-target-feature" "+sve2-sha3" // RUN: %clang --target=aarch64-linux-gnu -march=armv8-a+sve-aes %s -### 2>&1 | FileCheck %s --check-prefix=SVE-AES // SVE-AES: "-target-feature" "+aes"{{.*}} "-target-feature" "+sve-aes" diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-fujitsu-monaka.c b/clang/test/Driver/print-enabled-extensions/aarch64-fujitsu-monaka.c index 29e9682d58700..8576edff9bcbe 100644 --- a/clang/test/Driver/print-enabled-extensions/aarch64-fujitsu-monaka.c +++ b/clang/test/Driver/print-enabled-extensions/aarch64-fujitsu-monaka.c @@ -70,7 +70,7 @@ // CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions // CHECK-NEXT: FEAT_SVE_AES, FEAT_SVE_PMULL128 Enable SVE AES and quadword SVE polynomial multiply instructions // CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions -// CHECK-NEXT: FEAT_SVE_SHA3 Enable SHA3 SVE2 instructions +// CHECK-NEXT: FEAT_SVE_SHA3 Enable SVE SHA3 instructions // CHECK-NEXT: FEAT_SVE_SM4 Enable SM4 SVE2 instructions // CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions // CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-grace.c b/clang/test/Driver/print-enabled-extensions/aarch64-grace.c index 739d86f1fae0f..bb24dfbbc0702 100644 --- a/clang/test/Driver/print-enabled-extensions/aarch64-grace.c +++ b/clang/test/Driver/print-enabled-extensions/aarch64-grace.c @@ -54,7 +54,7 @@ // CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions // CHECK-NEXT: FEAT_SVE_AES, FEAT_SVE_PMULL128 Enable SVE AES and quadword SVE polynomial multiply instructions // CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions -// CHECK-NEXT: FEAT_SVE_SHA3 Enable SHA3 SVE2 instructions +// CHECK-NEXT: FEAT_SVE_SHA3 Enable SVE SHA3 instructions // CHECK-NEXT: FEAT_SVE_SM4 Enable SM4 SVE2 instructions // CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions // CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-olympus.c b/clang/test/Driver/print-enabled-extensions/aarch64-olympus.c index 64106e583d5f8..0cfb9e1fb9817 100644 --- a/clang/test/Driver/print-enabled-extensions/aarch64-olympus.c +++ b/clang/test/Driver/print-enabled-extensions/aarch64-olympus.c @@ -70,7 +70,7 @@ // CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions // CHECK-NEXT: FEAT_SVE_AES, FEAT_SVE_PMULL128 Enable SVE AES and quadword SVE polynomial multiply instructions // CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions -// CHECK-NEXT: FEAT_SVE_SHA3 Enable SHA3 SVE2 instructions +// CHECK-NEXT: FEAT_SVE_SHA3 Enable SVE SHA3 instructions // CHECK-NEXT: FEAT_SVE_SM4 Enable SM4 SVE2 instructions // CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions // CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension diff --git a/clang/test/Driver/print-supported-extensions-aarch64.c b/clang/test/Driver/print-supported-extensions-aarch64.c index 539c1937a9712..af4db9944c2df 100644 --- a/clang/test/Driver/print-supported-extensions-aarch64.c +++ b/clang/test/Driver/print-supported-extensions-aarch64.c @@ -92,10 +92,11 @@ // CHECK-NEXT: sve-bfscale FEAT_SVE_BFSCALE Enable Armv9.6-A SVE BFloat16 scaling instructions // CHECK-NEXT: sve-bitperm FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions // CHECK-NEXT: sve-f16f32mm FEAT_SVE_F16F32MM Enable Armv9.6-A FP16 to FP32 Matrix Multiply +// CHECK-NEXT: sve-sha3 FEAT_SVE_SHA3 Enable SVE SHA3 instructions // CHECK-NEXT: sve2 FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions // CHECK-NEXT: sve2-aes Shorthand for +sve2+sve-aes // CHECK-NEXT: sve2-bitperm Shorthand for +sve2+sve-bitperm -// CHECK-NEXT: sve2-sha3 FEAT_SVE_SHA3 Enable SHA3 SVE2 instructions +// CHECK-NEXT: sve2-sha3 Shorthand for +sve2+sve-sha3 // CHECK-NEXT: sve2-sm4 FEAT_SVE_SM4 Enable SM4 SVE2 instructions // CHECK-NEXT: sve2p1 FEAT_SVE2p1 Enable Scalable Vector Extension 2.1 instructions // CHECK-NEXT: sve2p2 FEAT_SVE2p2 Enable Armv9.6-A Scalable Vector Extension 2.2 instructions diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index eb5a5199b8951..aa2a177d88c5b 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -63,7 +63,7 @@ def SVE2p1Unsupported : AArch64Unsupported; def SVE2Unsupported : AArch64Unsupported { let F = !listconcat([HasSVE2, HasSVE2_or_SME, HasSVE2_or_SME2, HasSSVE_FP8FMA, HasSMEF8F16, - HasSMEF8F32, HasSVEAES, HasSVE2SHA3, HasSVE2SM4, HasSVEBitPerm, + HasSMEF8F32, HasSVEAES, HasSVESHA3, HasSVE2SM4, HasSVEBitPerm, HasSVEB16B16], SVE2p1Unsupported.F); } @@ -80,14 +80,14 @@ def SME2p2Unsupported : AArch64Unsupported; def SME2p1Unsupported : AArch64Unsupported { let F = !listconcat([HasSME2p1, HasSVE2p1_or_SME2p1, HasSME_MOP4, HasSME_TMOP, HasNonStreamingSVE_or_SSVE_FEXPA, - HasNonStreamingSVE2_or_SSVE_BitPerm], + HasNonStreamingSVE_or_SSVE_BitPerm], SME2p2Unsupported.F); } def SME2Unsupported : AArch64Unsupported { let F = !listconcat([HasSME2, HasSVE2_or_SME2, HasSVE2p1_or_SME2, HasSSVE_FP8FMA, HasSMEF8F16, HasSMEF8F32, HasSMEF16F16_or_SMEF8F16, HasSMEB16B16, - HasNonStreamingSVE2_or_SSVE_AES], + HasNonStreamingSVE_or_SSVE_AES], SME2p1Unsupported.F); } diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td index 469c76752c78c..538a142118a89 100644 --- a/llvm/lib/Target/AArch64/AArch64Features.td +++ b/llvm/lib/Target/AArch64/AArch64Features.td @@ -373,8 +373,11 @@ def FeatureAliasSVE2AES : ExtensionWithMArch<"sve2-aes", "SVE2AES", def FeatureSVE2SM4 : ExtensionWithMArch<"sve2-sm4", "SVE2SM4", "FEAT_SVE_SM4", "Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>; -def FeatureSVE2SHA3 : ExtensionWithMArch<"sve2-sha3", "SVE2SHA3", "FEAT_SVE_SHA3", - "Enable SHA3 SVE2 instructions", [FeatureSVE2, FeatureSHA3]>; +def FeatureSVESHA3 : ExtensionWithMArch<"sve-sha3", "SVESHA3", "FEAT_SVE_SHA3", + "Enable SVE SHA3 instructions", [FeatureSHA3]>; + +def FeatureAliasSVE2SHA3 : ExtensionWithMArch<"sve2-sha3", "SVE2SHA3", + "", "Shorthand for +sve2+sve-sha3", [FeatureSVE2, FeatureSVESHA3]>; def FeatureSVEBitPerm : ExtensionWithMArch<"sve-bitperm", "SVEBitPerm", "FEAT_SVE_BitPerm", "Enable bit permutation SVE2 instructions">; diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 0f3f24f0853c9..f01b634f44ba6 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -153,8 +153,8 @@ def HasSVEAES : Predicate<"Subtarget->hasSVEAES()">, AssemblerPredicateWithAll<(all_of FeatureSVEAES), "sve-aes">; def HasSVE2SM4 : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE2SM4()">, AssemblerPredicateWithAll<(all_of FeatureSVE2SM4), "sve2-sm4">; -def HasSVE2SHA3 : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE2SHA3()">, - AssemblerPredicateWithAll<(all_of FeatureSVE2SHA3), "sve2-sha3">; +def HasSVESHA3 : Predicate<"Subtarget->hasSVESHA3()">, + AssemblerPredicateWithAll<(all_of FeatureSVESHA3), "sve-sha3">; def HasSVEBitPerm : Predicate<"Subtarget->hasSVEBitPerm()">, AssemblerPredicateWithAll<(all_of FeatureSVEBitPerm), "sve-bitperm">; def HasSMEandIsNonStreamingSafe @@ -248,11 +248,26 @@ def HasSVE_or_SME : Predicate<"Subtarget->isSVEorStreamingSVEAvailable()">, AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME), "sve or sme">; +def HasNonStreamingSVE_or_SME2p1 + : Predicate<"Subtarget->isSVEAvailable() ||" + "(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p1())">, + AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME2p1), + "sve or sme2p1">; def HasNonStreamingSVE_or_SME2p2 : Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE()) ||" "(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p2())">, AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME2p2), "sve or sme2p2">; +def HasNonStreamingSVE_or_SSVE_AES + : Predicate<"Subtarget->isSVEAvailable() ||" + "(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_AES())">, + AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSSVE_AES), + "sve or ssve-aes">; +def HasNonStreamingSVE_or_SSVE_BitPerm + : Predicate<"Subtarget->isSVEAvailable() ||" + "(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_BitPerm())">, + AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSSVE_BitPerm), + "sve or ssve-bitperm">; def HasNonStreamingSVE_or_SSVE_FEXPA : Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE()) ||" "(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_FEXPA())">, @@ -267,11 +282,6 @@ def HasSVE2_or_SME2 : Predicate<"Subtarget->hasSVE2() || (Subtarget->isStreaming() && Subtarget->hasSME2())">, AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSME2), "sve2 or sme2">; -def HasNonStreamingSVE2_or_SSVE_AES - : Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE2()) ||" - "(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_AES())">, - AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSSVE_AES), - "sve2 or ssve-aes">; def HasSVE2p1_or_SME : Predicate<"Subtarget->hasSVE2p1() || (Subtarget->isStreaming() && Subtarget->hasSME())">, @@ -300,11 +310,6 @@ def HasSMEF16F16_or_SMEF8F16 : Predicate<"Subtarget->isStreaming() && (Subtarget->hasSMEF16F16() || Subtarget->hasSMEF8F16())">, AssemblerPredicateWithAll<(any_of FeatureSMEF16F16, FeatureSMEF8F16), "sme-f16f16 or sme-f8f16">; -def HasNonStreamingSVE2_or_SSVE_BitPerm - : Predicate<"(Subtarget->isSVEAvailable() && Subtarget->hasSVE2()) ||" - "(Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSSVE_BitPerm())">, - AssemblerPredicateWithAll<(any_of FeatureSVE2, FeatureSSVE_BitPerm), - "sve2 or ssve-bitperm">; // A subset of NEON instructions are legal in Streaming SVE execution mode, // so don't need the additional check for 'isNeonAvailable'. diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index e1b82953aad80..ad041788e4d5d 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -897,7 +897,7 @@ def ProcessorFeatures { FeatureFPAC, FeatureFP16FML, FeatureRandGen, FeatureSSBS, FeatureLS64, FeatureCLRBHB, FeatureSPECRES2, FeatureSVEAES, FeatureSVE2SM4, - FeatureSVE2SHA3, FeatureSVE2, FeatureSVEBitPerm, FeatureETE, + FeatureSVESHA3, FeatureSVE2, FeatureSVEBitPerm, FeatureETE, FeatureMEC, FeatureFAMINMAX, FeatureFP8DOT2, FeatureFP8DOT4, FeatureFP8FMA, FeatureLUT]; list<SubtargetFeature> Carmel = [HasV8_2aOps, FeatureNEON, FeatureSHA2, FeatureAES, @@ -910,7 +910,7 @@ def ProcessorFeatures { FeatureLS64, FeatureLUT, FeatureMEC, FeatureMTE, FeaturePerfMon, FeatureRandGen, FeatureSPE, FeatureSPE_EEF, FeatureSSBS, - FeatureSVEBitPerm, FeatureSVE2SHA3, + FeatureSVEBitPerm, FeatureSVESHA3, FeatureSVE2SM4, FeatureSVEAES]; list<SubtargetFeature> AppleA7 = [HasV8_0aOps, FeatureSHA2, FeatureAES, FeatureFPARMv8, FeatureNEON,FeaturePerfMon]; @@ -1107,7 +1107,7 @@ def ProcessorFeatures { FeatureDotProd, FeatureFPARMv8, FeatureMatMulInt8, FeatureSSBS, FeatureCCIDX, FeatureJS, FeatureLSE, FeatureRAS, FeatureRCPC, FeatureRDM]; - list<SubtargetFeature> Grace = !listconcat(NeoverseV2, [FeatureSVE2SM4, FeatureSVEAES, FeatureSVE2SHA3]); + list<SubtargetFeature> Grace = !listconcat(NeoverseV2, [FeatureSVE2SM4, FeatureSVEAES, FeatureSVESHA3]); // ETE and TRBE are future architecture extensions. We temporarily enable them // by default for users targeting generic AArch64. The extensions do not diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 2360e30de63b0..af56f6a876221 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -4062,7 +4062,7 @@ let Predicates = [HasSVE2_or_SME] in { defm WHILERW_PXX : sve2_int_while_rr<0b1, "whilerw", "int_aarch64_sve_whilerw">; } // End HasSVE2_or_SME -let Predicates = [HasSVEAES, HasNonStreamingSVE2_or_SSVE_AES] in { +let Predicates = [HasSVEAES, HasNonStreamingSVE_or_SSVE_AES] in { // SVE2 crypto destructive binary operations let isCommutable = 1 in { def AESE_ZZZ_B : sve2_crypto_des_bin_op<0b00, "aese", ZPR8, int_aarch64_sve_aese, nxv16i8>; @@ -4087,19 +4087,19 @@ let Predicates = [HasSVE2SM4] in { def SM4E_ZZZ_S : sve2_crypto_des_bin_op<0b10, "sm4e", ZPR32, int_aarch64_sve_sm4e, nxv4i32>; } // End HasSVE2SM4 -let Predicates = [HasSVE2SHA3] in { +let Predicates = [HasSVESHA3, HasNonStreamingSVE_or_SME2p1] in { // SVE2 crypto constructive binary operations defm RAX1_ZZZ_D : sve2_crypto_cons_bin_op<0b1, "rax1", ZPR64, int_aarch64_sve_rax1, nxv2i64>; -} // End HasSVE2SHA3 +} // End HasSVESHA3, HasNonStreamingSVE_or_SME2p1 -let Predicates = [HasSVEBitPerm, HasNonStreamingSVE2_or_SSVE_BitPerm] in { +let Predicates = [HasSVEBitPerm, HasNonStreamingSVE_or_SSVE_BitPerm] in { // SVE2 bitwise permute defm BEXT_ZZZ : sve2_misc_bitwise<0b1100, "bext", int_aarch64_sve_bext_x>; defm BDEP_ZZZ : sve2_misc_bitwise<0b1101, "bdep", int_aarch64_sve_bdep_x>; defm BGRP_ZZZ : sve2_misc_bitwise<0b1110, "bgrp", int_aarch64_sve_bgrp_x>; } -let Predicates = [HasSVEAES2, HasNonStreamingSVE2_or_SSVE_AES] in { +let Predicates = [HasSVEAES2, HasNonStreamingSVE_or_SSVE_AES] in { // SVE_AES2 multi-vector instructions (x2) def AESE_2ZZI_B : sve_crypto_binary_multi2<0b000, "aese">; def AESD_2ZZI_B : sve_crypto_binary_multi2<0b010, "aesd">; diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp index faa82abbd898a..214d6fe246d98 100644 --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -3752,7 +3752,8 @@ static const struct Extension { {"sve-aes", {AArch64::FeatureSVEAES}}, {"sve2-aes", {AArch64::FeatureAliasSVE2AES, AArch64::FeatureSVEAES}}, {"sve2-sm4", {AArch64::FeatureSVE2SM4}}, - {"sve2-sha3", {AArch64::FeatureSVE2SHA3}}, + {"sve-sha3", {AArch64::FeatureSVESHA3}}, + {"sve2-sha3", {AArch64::FeatureAliasSVE2SHA3, AArch64::FeatureSVESHA3}}, {"sve-bitperm", {AArch64::Fea... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/145696 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
