================ @@ -0,0 +1,11 @@ +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +zvknha %s -fsyntax-only -verify + +#include <riscv_vector.h> + +// expected-no-diagnostics + +__attribute__((target("arch=+zvl128b"))) +void test_zvk_features(vuint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) { ---------------- 4vtomat wrote:
We'll have following error: `RISC-V type 'vuint32m1_t' (aka '__rvv_uint32m1_t') requires the 'zvl128b' extension` That's the extra check for vector crypto extensions https://github.com/llvm/llvm-project/pull/141548 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits