https://github.com/Ami-zhang updated
https://github.com/llvm/llvm-project/pull/141192
>From 6f3c80398e05ead828af2bac844992df8d8f5699 Mon Sep 17 00:00:00 2001
From: Ami-zhang <zhangli...@loongson.cn>
Date: Fri, 23 May 2025 10:21:00 +0800
Subject: [PATCH] [Options] Add same-address constraint to the description of
'-m[no]ld-seq-sa'
Also, remove redundant "." in feature descriptions.
---
clang/include/clang/Driver/Options.td | 4 ++--
llvm/lib/Target/LoongArch/LoongArch.td | 8 ++++----
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index 22261621df092..6226444af2d9a 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -5526,9 +5526,9 @@ def mlamcas : Flag<["-"], "mlamcas">,
Group<m_loongarch_Features_Group>,
def mno_lamcas : Flag<["-"], "mno-lamcas">, Group<m_loongarch_Features_Group>,
HelpText<"Disable amcas[_db].{b/h/w/d}">;
def mld_seq_sa : Flag<["-"], "mld-seq-sa">, Group<m_loongarch_Features_Group>,
- HelpText<"Do not generate load-load barrier instructions (dbar 0x700)">;
+ HelpText<"Do not generate same-address load-load barrier instructions (dbar
0x700)">;
def mno_ld_seq_sa : Flag<["-"], "mno-ld-seq-sa">,
Group<m_loongarch_Features_Group>,
- HelpText<"Generate load-load barrier instructions (dbar 0x700)">;
+ HelpText<"Generate same-address load-load barrier instructions (dbar
0x700)">;
def mdiv32 : Flag<["-"], "mdiv32">, Group<m_loongarch_Features_Group>,
HelpText<"Use div.w[u] and mod.w[u] instructions with input not
sign-extended.">;
def mno_div32 : Flag<["-"], "mno-div32">, Group<m_loongarch_Features_Group>,
diff --git a/llvm/lib/Target/LoongArch/LoongArch.td
b/llvm/lib/Target/LoongArch/LoongArch.td
index 1d3dc3342a192..39948b31fb9b9 100644
--- a/llvm/lib/Target/LoongArch/LoongArch.td
+++ b/llvm/lib/Target/LoongArch/LoongArch.td
@@ -118,24 +118,24 @@ def FeatureRelax
// Floating point approximation operation
def FeatureFrecipe
: SubtargetFeature<"frecipe", "HasFrecipe", "true",
- "Support frecipe.{s/d} and frsqrte.{s/d}
instructions.">;
+ "Support frecipe.{s/d} and frsqrte.{s/d} instructions">;
def HasFrecipe : Predicate<"Subtarget->hasFrecipe()">;
// Atomic memory swap and add instructions for byte and half word
def FeatureLAM_BH
: SubtargetFeature<"lam-bh", "HasLAM_BH", "true",
- "Support amswap[_db].{b/h} and amadd[_db].{b/h}
instructions.">;
+ "Support amswap[_db].{b/h} and amadd[_db].{b/h}
instructions">;
def HasLAM_BH : Predicate<"Subtarget->hasLAM_BH()">;
// Atomic memory compare and swap instructions for byte, half word, word and
double word
def FeatureLAMCAS
: SubtargetFeature<"lamcas", "HasLAMCAS", "true",
- "Support amcas[_db].{b/h/w/d}.">;
+ "Support amcas[_db].{b/h/w/d}">;
def HasLAMCAS : Predicate<"Subtarget->hasLAMCAS()">;
def FeatureLD_SEQ_SA
: SubtargetFeature<"ld-seq-sa", "HasLD_SEQ_SA", "true",
- "Don't use load-load barrier (dbar 0x700).">;
+ "Don't use a same-address load-load barrier (dbar
0x700)">;
def HasLD_SEQ_SA : Predicate<"Subtarget->hasLD_SEQ_SA()">;
// Assume div.w[u] and mod.w[u] can handle inputs that are not sign-extended.
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