https://github.com/heiher updated https://github.com/llvm/llvm-project/pull/141037
>From 1148711cdfdd5a58960564790509559fa86e2649 Mon Sep 17 00:00:00 2001 From: WANG Rui <wang...@loongson.cn> Date: Thu, 22 May 2025 09:59:53 +0800 Subject: [PATCH 1/5] [Clang][LoongArch] Add inline asm support for the `q` constraint This patch adds support for the `q` constraint: a general-purpose register except for $r0 and $r1 (for the csrxchg instruction) Link: https://gcc.gnu.org/pipermail/gcc-patches/2025-May/684339.html --- clang/lib/Basic/Targets/LoongArch.cpp | 5 +++++ .../test/CodeGen/LoongArch/inline-asm-constraints.c | 6 ++++++ llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp | 5 +++++ llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll | 12 ++++++++++++ 4 files changed, 28 insertions(+) diff --git a/clang/lib/Basic/Targets/LoongArch.cpp b/clang/lib/Basic/Targets/LoongArch.cpp index ca742797d7a3b..f4bcb54bd470d 100644 --- a/clang/lib/Basic/Targets/LoongArch.cpp +++ b/clang/lib/Basic/Targets/LoongArch.cpp @@ -139,6 +139,11 @@ bool LoongArchTargetInfo::validateAsmConstraint( // A signed 16-bit constant. Info.setRequiresImmediate(-32768, 32767); return true; + case 'q': + // A general-purpose register except for $r0 and $r1 (for the csrxchg + // instruction) + Info.setAllowsRegister(); + return true; case 'I': // A signed 12-bit constant (for arithmetic instructions). Info.setRequiresImmediate(-2048, 2047); diff --git a/clang/test/CodeGen/LoongArch/inline-asm-constraints.c b/clang/test/CodeGen/LoongArch/inline-asm-constraints.c index b19494284bd99..ded21206d63bf 100644 --- a/clang/test/CodeGen/LoongArch/inline-asm-constraints.c +++ b/clang/test/CodeGen/LoongArch/inline-asm-constraints.c @@ -35,6 +35,12 @@ void test_m(int *p) { asm volatile("" :: "m"(*(p+4))); } +void test_q(void) { +// CHECK-LABEL: define{{.*}} void @test_q() +// CHECK: call void asm sideeffect "", "q"(i32 0) + asm volatile ("" :: "q"(0)); +} + void test_I(void) { // CHECK-LABEL: define{{.*}} void @test_I() // CHECK: call void asm sideeffect "", "I"(i32 2047) diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp index 9774683e16291..50ec0b2e3ca78 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp @@ -7276,6 +7276,8 @@ LoongArchTargetLowering::getConstraintType(StringRef Constraint) const { // 'm': A memory operand whose address is formed by a base register and // offset that is suitable for use in instructions with the same // addressing mode as st.w and ld.w. + // 'q': A general-purpose register except for $r0 and $r1 (for the csrxchg + // instruction) // 'I': A signed 12-bit constant (for arithmetic instructions). // 'J': Integer zero. // 'K': An unsigned 12-bit constant (for logic instructions). @@ -7289,6 +7291,7 @@ LoongArchTargetLowering::getConstraintType(StringRef Constraint) const { default: break; case 'f': + case 'q': return C_RegisterClass; case 'l': case 'I': @@ -7328,6 +7331,8 @@ LoongArchTargetLowering::getRegForInlineAsmConstraint( if (VT.isVector()) break; return std::make_pair(0U, &LoongArch::GPRRegClass); + case 'q': + return std::make_pair(0U, &LoongArch::GPRNoR0R1RegClass); case 'f': if (Subtarget.hasBasicF() && VT == MVT::f32) return std::make_pair(0U, &LoongArch::FPR32RegClass); diff --git a/llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll b/llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll index 4bcc88be97396..73d240b99b0bc 100644 --- a/llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll +++ b/llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll @@ -17,6 +17,18 @@ define i32 @constraint_r(i32 %a, i32 %b) nounwind { ret i32 %1 } +define i32 @constraint_q(i32 %a) nounwind { +; CHECK-LABEL: constraint_q: +; CHECK: # %bb.0: +; CHECK-NEXT: move $a1, $zero +; CHECK-NEXT: #APP +; CHECK-NEXT: csrxchg $a0, $a1, 0 +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: ret + %1 = tail call i32 asm "csrxchg $0, $1, $2", "=r,q,i,0"(i32 0, i32 0, i32 %a) + ret i32 %1 +} + define i32 @constraint_i(i32 %a) nounwind { ; CHECK-LABEL: constraint_i: ; CHECK: # %bb.0: >From 5c7090293bb9ace8f1d81c1b8e8d9f04b6f42682 Mon Sep 17 00:00:00 2001 From: WANG Rui <wang...@loongson.cn> Date: Thu, 22 May 2025 19:21:20 +0800 Subject: [PATCH 2/5] Address xen0n's comments --- .../LoongArch/inline-asm-constraint-q.ll | 20 +++++++++++++++++++ .../LoongArch/inline-asm-constraint.ll | 12 ----------- 2 files changed, 20 insertions(+), 12 deletions(-) create mode 100644 llvm/test/CodeGen/LoongArch/inline-asm-constraint-q.ll diff --git a/llvm/test/CodeGen/LoongArch/inline-asm-constraint-q.ll b/llvm/test/CodeGen/LoongArch/inline-asm-constraint-q.ll new file mode 100644 index 0000000000000..f22fecdd16829 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/inline-asm-constraint-q.ll @@ -0,0 +1,20 @@ +; RUN: llc --mtriple=loongarch32 --mattr=+f --verify-machineinstrs < %s | FileCheck %s +; RUN: llc --mtriple=loongarch64 --mattr=+f --verify-machineinstrs < %s | FileCheck %s + +;; Check that the "q" operand is not R0. +define i32 @constraint_q_not_r0(i32 %a) { +; CHECK-NOT: csrxchg ${{[a-z]*}}, $r0, 0 +; CHECK-NOT: csrxchg ${{[a-z]*}}, $zero, 0 +entry: + %1 = tail call i32 asm "csrxchg $0, $1, $2", "=r,q,i,0"(i32 0, i32 0, i32 %a) + ret i32 %1 +} + +;; Check that the "q" operand is not R1. +define i32 @constraint_q_not_r1() { +; CHECK-NOT: csrxchg ${{[a-z]*}}, $r1, 0 +; CHECK-NOT: csrxchg ${{[a-z]*}}, $ra, 0 +entry: + %0 = tail call i32 asm "csrxchg $0, $1, $2", "=r,q,i,{r4},{r5},{r6},{r7},{r8},{r9},{r10},{r11},{r12},{r13},{r14},{r15},{r16},{r17},{r18},{r19},{r20},{r23},{r24},{r25},{r26},{r27},{r28},{r29},{r30},{r31},0"(i32 4, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + ret i32 %0 +} diff --git a/llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll b/llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll index 73d240b99b0bc..4bcc88be97396 100644 --- a/llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll +++ b/llvm/test/CodeGen/LoongArch/inline-asm-constraint.ll @@ -17,18 +17,6 @@ define i32 @constraint_r(i32 %a, i32 %b) nounwind { ret i32 %1 } -define i32 @constraint_q(i32 %a) nounwind { -; CHECK-LABEL: constraint_q: -; CHECK: # %bb.0: -; CHECK-NEXT: move $a1, $zero -; CHECK-NEXT: #APP -; CHECK-NEXT: csrxchg $a0, $a1, 0 -; CHECK-NEXT: #NO_APP -; CHECK-NEXT: ret - %1 = tail call i32 asm "csrxchg $0, $1, $2", "=r,q,i,0"(i32 0, i32 0, i32 %a) - ret i32 %1 -} - define i32 @constraint_i(i32 %a) nounwind { ; CHECK-LABEL: constraint_i: ; CHECK: # %bb.0: >From d1f23ba457fe3f11526558f07f913d25dd94ce44 Mon Sep 17 00:00:00 2001 From: WANG Rui <wang...@loongson.cn> Date: Thu, 22 May 2025 19:34:11 +0800 Subject: [PATCH 3/5] Update inline-asm-constraint-q test case --- llvm/test/CodeGen/LoongArch/inline-asm-constraint-q.ll | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/test/CodeGen/LoongArch/inline-asm-constraint-q.ll b/llvm/test/CodeGen/LoongArch/inline-asm-constraint-q.ll index f22fecdd16829..b753ab7170cb3 100644 --- a/llvm/test/CodeGen/LoongArch/inline-asm-constraint-q.ll +++ b/llvm/test/CodeGen/LoongArch/inline-asm-constraint-q.ll @@ -2,11 +2,11 @@ ; RUN: llc --mtriple=loongarch64 --mattr=+f --verify-machineinstrs < %s | FileCheck %s ;; Check that the "q" operand is not R0. -define i32 @constraint_q_not_r0(i32 %a) { +define i32 @constraint_q_not_r0() { ; CHECK-NOT: csrxchg ${{[a-z]*}}, $r0, 0 ; CHECK-NOT: csrxchg ${{[a-z]*}}, $zero, 0 entry: - %1 = tail call i32 asm "csrxchg $0, $1, $2", "=r,q,i,0"(i32 0, i32 0, i32 %a) + %1 = tail call i32 asm "csrxchg $0, $1, $2", "=r,q,i,0"(i32 0, i32 0, i32 0) ret i32 %1 } >From 8c0f60464690a10f03336dcf36392efaf294f38d Mon Sep 17 00:00:00 2001 From: WANG Rui <wang...@loongson.cn> Date: Thu, 22 May 2025 20:20:46 +0800 Subject: [PATCH 4/5] Took xry's idea --- .../test/CodeGen/LoongArch/inline-asm-constraint-q.ll | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/llvm/test/CodeGen/LoongArch/inline-asm-constraint-q.ll b/llvm/test/CodeGen/LoongArch/inline-asm-constraint-q.ll index b753ab7170cb3..cc730936ff882 100644 --- a/llvm/test/CodeGen/LoongArch/inline-asm-constraint-q.ll +++ b/llvm/test/CodeGen/LoongArch/inline-asm-constraint-q.ll @@ -6,15 +6,16 @@ define i32 @constraint_q_not_r0() { ; CHECK-NOT: csrxchg ${{[a-z]*}}, $r0, 0 ; CHECK-NOT: csrxchg ${{[a-z]*}}, $zero, 0 entry: - %1 = tail call i32 asm "csrxchg $0, $1, $2", "=r,q,i,0"(i32 0, i32 0, i32 0) - ret i32 %1 + %2 = tail call i32 asm "csrxchg $0, $1, 0", "=r,q,0"(i32 0, i32 0) + ret i32 %2 } ;; Check that the "q" operand is not R1. -define i32 @constraint_q_not_r1() { +define i32 @constraint_q_not_r1(i32 %0) { ; CHECK-NOT: csrxchg ${{[a-z]*}}, $r1, 0 ; CHECK-NOT: csrxchg ${{[a-z]*}}, $ra, 0 entry: - %0 = tail call i32 asm "csrxchg $0, $1, $2", "=r,q,i,{r4},{r5},{r6},{r7},{r8},{r9},{r10},{r11},{r12},{r13},{r14},{r15},{r16},{r17},{r18},{r19},{r20},{r23},{r24},{r25},{r26},{r27},{r28},{r29},{r30},{r31},0"(i32 4, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) - ret i32 %0 + %2 = tail call i32 asm "", "={$r1},{$r1}"(i32 undef) + %3 = tail call i32 asm "csrxchg $0, $1, 0", "=r,q,0"(i32 %2, i32 %0) + ret i32 %3 } >From e190b127fbae6f64449f8cf9f57aa030f4d233ce Mon Sep 17 00:00:00 2001 From: WANG Rui <wang...@loongson.cn> Date: Thu, 22 May 2025 20:35:47 +0800 Subject: [PATCH 5/5] Drop uses of `udef` --- llvm/test/CodeGen/LoongArch/inline-asm-constraint-q.ll | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/test/CodeGen/LoongArch/inline-asm-constraint-q.ll b/llvm/test/CodeGen/LoongArch/inline-asm-constraint-q.ll index cc730936ff882..e16bd1d8aacf3 100644 --- a/llvm/test/CodeGen/LoongArch/inline-asm-constraint-q.ll +++ b/llvm/test/CodeGen/LoongArch/inline-asm-constraint-q.ll @@ -15,7 +15,7 @@ define i32 @constraint_q_not_r1(i32 %0) { ; CHECK-NOT: csrxchg ${{[a-z]*}}, $r1, 0 ; CHECK-NOT: csrxchg ${{[a-z]*}}, $ra, 0 entry: - %2 = tail call i32 asm "", "={$r1},{$r1}"(i32 undef) + %2 = tail call i32 asm "", "={$r1},{$r1}"(i32 0) %3 = tail call i32 asm "csrxchg $0, $1, 0", "=r,q,0"(i32 %2, i32 %0) ret i32 %3 } _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
