Author: Jim Lin Date: 2025-05-22T14:41:58+08:00 New Revision: 04211ba7274ba85dd762a2c919f633f792fa9a3c
URL: https://github.com/llvm/llvm-project/commit/04211ba7274ba85dd762a2c919f633f792fa9a3c DIFF: https://github.com/llvm/llvm-project/commit/04211ba7274ba85dd762a2c919f633f792fa9a3c.diff LOG: [RISCV] Add FeatureVendorXAndesPerf to Andes N45/NX45/A45/AX45 (#141007) Andes N45/NX45/A45/AX45 also support XAndesPerf. Added: Modified: clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c clang/test/Driver/print-enabled-extensions/riscv-andes-nx45.c llvm/lib/Target/RISCV/RISCVProcessors.td Removed: ################################################################################ diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c index b1cecfbb0ff32..a0a1c35911409 100644 --- a/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c +++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c @@ -22,7 +22,8 @@ // CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) // CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) // CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) +// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension) // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions // CHECK-EMPTY: -// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbs1p0 +// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0 diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c index a47e7f0cbd05f..6460d701411bc 100644 --- a/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c +++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c @@ -21,7 +21,8 @@ // CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) // CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) // CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) +// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension) // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions // CHECK-EMPTY: -// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbs1p0 +// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0 diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c index fa4ceb8b13c0e..4d9c514b756e6 100644 --- a/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c +++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c @@ -22,7 +22,8 @@ // CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) // CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) // CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) +// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension) // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions // CHECK-EMPTY: -// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbs1p0 +// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0 diff --git a/clang/test/Driver/print-enabled-extensions/riscv-andes-nx45.c b/clang/test/Driver/print-enabled-extensions/riscv-andes-nx45.c index fdb3be3d38073..5eaada3f9e164 100644 --- a/clang/test/Driver/print-enabled-extensions/riscv-andes-nx45.c +++ b/clang/test/Driver/print-enabled-extensions/riscv-andes-nx45.c @@ -21,7 +21,8 @@ // CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) // CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) // CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) +// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension) // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions // CHECK-EMPTY: -// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbs1p0 +// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbs1p0_xandesperf5p0 diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 419609807bda9..dc0ae384d6b08 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -689,7 +689,8 @@ def ANDES_N45 : RISCVProcessorModel<"andes-n45", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC, - FeatureStdExtB]>; + FeatureStdExtB, + FeatureVendorXAndesPerf]>; def ANDES_NX45 : RISCVProcessorModel<"andes-nx45", NoSchedModel, @@ -702,7 +703,8 @@ def ANDES_NX45 : RISCVProcessorModel<"andes-nx45", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC, - FeatureStdExtB]>; + FeatureStdExtB, + FeatureVendorXAndesPerf]>; def ANDES_A45 : RISCVProcessorModel<"andes-a45", NoSchedModel, @@ -715,7 +717,8 @@ def ANDES_A45 : RISCVProcessorModel<"andes-a45", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC, - FeatureStdExtB]>; + FeatureStdExtB, + FeatureVendorXAndesPerf]>; def ANDES_AX45 : RISCVProcessorModel<"andes-ax45", NoSchedModel, @@ -728,4 +731,5 @@ def ANDES_AX45 : RISCVProcessorModel<"andes-ax45", FeatureStdExtF, FeatureStdExtD, FeatureStdExtC, - FeatureStdExtB]>; + FeatureStdExtB, + FeatureVendorXAndesPerf]>; _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
