================ @@ -674,6 +681,9 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) { Opcode = RISCV::FSD; IsScalableVector = false; + } else if (RISCV::FPR128RegClass.hasSubClassEq(RC)) { ---------------- el-ev wrote:
Removed, thanks. https://github.com/llvm/llvm-project/pull/139369 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits